US3906200A
Expired / Lapsed
US
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Error logging in semiconductor storage units
Assignee: Unisys Corp
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Filing: 1974-07-05
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Granted: 1975-09-16
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Expires: 1994-07-05
Abstract
Abstract A maintenance procedure comprising a method of and an apparatus for storing information identifying the location of one or more defective bits, i.e., a defective memory element, a defective storage device or a failure, in a single-error-correcting semiconductor main storage unit (MSU) comprised of a plurality of large scale integrated (LSI) bit planes. The method utilizes an error logging store (ELS) comprised of 128 word-group-associated memory registers, each memory register storing 1 tag bit and 6 syndrome bits. Upon determination of a single bit error during the readout of a word from the MSU, stored in the ELS are: (1) a tag bit that when set signifies that a defective bit has been determined to be in the one associated word group; and, (2) a group of 6 syndrome bits that identifies the one of the 45, 1024 bit planes of the one associated word group that contains the defective bit. A defective device counter (DDC) counts the set tag bits in the ELS and is utilized by the machine operator to schedule preventative maintenance of the MSU by replacing the defective bit planes. By statistically determining the number of allowable failures, i.e., the number of correctable failures that may occur before the expected occurrence of a noncorrectable double bit error, preventative maintenance may be scheduled only as required by the particular MSU.
Inventors
- 👤 Richard J Petschauer
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 12:43
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/0703; G06F11/0766; G06F11/0772; G06F11/0706; G06F11/073; G06F11/0751; G06F11/0754; G06F11/076; G06F11/0787; G11; G11C; G11C7/00; G11C7/24
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
220 words
In a procedure for scheduling preventative maintenance in a memory system that is configured into N bit planes and B bits per bit plane, each bit plane being a replaceable component that is replaced upon the detection of a defective device or bit therein, the method comprising: arranging an error logging store to be comprised of a plurality of memory registers, each memory register representing an associated different one of said bit planes; generating, upon the detection of a defective device in each bit plane, an error word that is associated with the bit plane in which the defective device is detected, said error word comprising a single tag bit; testing the bit that is stored in the tag bit position of the memory register that is associated with the bit plane with which the generated error word is associated; storing said generated error word in its associated one memory register of said error logging store; generating a defective device count only if said test indicates that an error has not previously occurred in the associated one of said bit planes; incrementing a defective device counter only upon the generation of each of said defective device counts; monitoring said defective device counter; and, scheduling preventative maintenance of said memory system when said monitored defective device count reaches a predetermined magnitude.
Claim 2
Dependent Claim
220 words
In a procedure for scheduling preventative maintenance in a memory system that is configured into N bit planes and B bits per bit plane, each bit plane being a replaceable component that is replaced upon the detection of a defective device or bit therein, the method comprising: arranging an error logging store to be comprised of a plurality of memory registers, each memory register representing an associated different one of said bit planes; generating, upon the detection of a defective device in each bit plane, an error word that is associated with the bit plane in which the defective device is detected, said error word comprising a single tag bit; testing the bit that is stored in the tag bit position of the memory register that is associated with the bit plane with which the generated error word is associated; storing said generated error word in its associated one memory register of said error logging store; generating a defective device count only if said test indicates that an error has not previously occurred in the associated one of said bit planes; incrementing a defective device counter only upon the generation of each of said defective device counts; monitoring said defective device counter; and, scheduling preventative maintenance of said memory system when said monitored defective device count reaches a predetermined magnitude.
Claim 3
Dependent Claim
312 words
In a procedure for scheduling preventative maintenance in a single error correction memory system that is configured into M word groups of N bit planes per word group and B bits per bit plane, each bit plane being a replaceable component upon the detection of a single defective device or bit therein that provides a correctable error upon readout, the method comprising: arranging an error logging store to be comprised of M memory registers, each memory register dedicated to represent only an associated different one of said M word groups; generating upon the detection of each correctable error a generated error word that is associated with the one of the M word group in which the correctable error is detected, said generated error word comprising a single tag bit and a plurality of syndrome bits, said tag bit indicating that a correctable error has occurred in said one of M word groups in the one of N bit planes that is identified by said syndrome bits; comparing the tag bit of the generated error word to the bit that is stored in the tag bit position of the one of M memory registers that is dedicated to the one of M word groups to which the generated error word is associated; storing said generated error word in its associated one of said M memory registers only if said comparison indicates that a correctable error has not previously occurred in the associated one of said M word groups; generating a defective device count only if said comparison indicates that a correctable error has not previously occurred in the associated one of said M word groups; incrementing a defective device counter upon the generation of each of said defective device counts; monitoring said defective device counter; and, scheduling preventative maintenance of said memory system when said monitored defective device count reaches a predetermined magnitude.
Claim 4
Dependent Claim
312 words
In a procedure for scheduling preventative maintenance in a single error correction memory system that is configured into M word groups of N bit planes per word group and B bits per bit plane, each bit plane being a replaceable component upon the detection of a single defective device or bit therein that provides a correctable error upon readout, the method comprising: arranging an error logging store to be comprised of M memory registers, each memory register dedicated to represent only an associated different one of said M word groups; generating upon the detection of each correctable error a generated error word that is associated with the one of the M word group in which the correctable error is detected, said generated error word comprising a single tag bit and a plurality of syndrome bits, said tag bit indicating that a correctable error has occurred in said one of M word groups in the one of N bit planes that is identified by said syndrome bits; comparing the tag bit of the generated error word to the bit that is stored in the tag bit position of the one of M memory registers that is dedicated to the one of M word groups to which the generated error word is associated; storing said generated error word in its associated one of said M memory registers only if said comparison indicates that a correctable error has not previously occurred in the associated one of said M word groups; generating a defective device count only if said comparison indicates that a correctable error has not previously occurred in the associated one of said M word groups; incrementing a defective device counter upon the generation of each of said defective device counts; monitoring said defective device counter; and, scheduling preventative maintenance of said memory system when said monitored defective device count reaches a predetermined magnitude.
Claim 5
Dependent Claim
301 words
In a procedure for schEduling preventative maintenance in a single error correction memory system that is configured into M word groups of N bit planes per word group and B bits per bit plane, each bit plane being a replaceable component upon the detection of a single defective device or bit therein that provides a correctable error upon readout, the method comprising: arranging an error logging store to be comprised of M memory registers, each memory register dedicated to represent only an associated different one of said M word groups; generating upon the detection of each correctable error a generated error word that is associated with the one of the M word groups in which the correctable error is detected, said generated error word comprising a single tag bit and a plurality of syndrome bits, said tag bit indicating that a correctable error has occurred in said one of M word groups in the one of N bit planes that is identified by said syndrome bits; testing the bit that is stored in the tag bit position of the one of M memory registers that is dedicated to the one of M word groups to which the generated error word is associated; storing said generated error word in its associated one of said M memory registers only if said test indicates that a correctable error has not previously occurred in the associated one of said M word groups; generating an error signal only if said test indicates that a correctable error has not previously occurred in the associated one of said M word groups; incrementing a defective device counter upon the generation of each of said error signals; monitoring said defective device counter; and scheduling preventative maintenance of said memory system when said monitored defective device count reaches a predetermined magnitude.
Claim 6
Dependent Claim
301 words
In a procedure for schEduling preventative maintenance in a single error correction memory system that is configured into M word groups of N bit planes per word group and B bits per bit plane, each bit plane being a replaceable component upon the detection of a single defective device or bit therein that provides a correctable error upon readout, the method comprising: arranging an error logging store to be comprised of M memory registers, each memory register dedicated to represent only an associated different one of said M word groups; generating upon the detection of each correctable error a generated error word that is associated with the one of the M word groups in which the correctable error is detected, said generated error word comprising a single tag bit and a plurality of syndrome bits, said tag bit indicating that a correctable error has occurred in said one of M word groups in the one of N bit planes that is identified by said syndrome bits; testing the bit that is stored in the tag bit position of the one of M memory registers that is dedicated to the one of M word groups to which the generated error word is associated; storing said generated error word in its associated one of said M memory registers only if said test indicates that a correctable error has not previously occurred in the associated one of said M word groups; generating an error signal only if said test indicates that a correctable error has not previously occurred in the associated one of said M word groups; incrementing a defective device counter upon the generation of each of said error signals; monitoring said defective device counter; and scheduling preventative maintenance of said memory system when said monitored defective device count reaches a predetermined magnitude.
Claim 7
Dependent Claim
299 words
In a data processing system that includes a memory system that is configured into N bit planes and B bits per bit plane, each bit plane being a replaceable component upon the detection of a single defective device or bit therein that provides an error upon readout, and error circuitry coupled to said memory system for generating, upon the detection of each of said errors in said memory system, an error word that is associated with only the one bit plane in which the error is detected, said error word comprising a single tag bit, said tag bit indicating that an error has occurred in said one bit plane, the improvement comprising: an error logging store comprised of a plurality of memory registers each memory register dedicated to represent only an associated different one of said bit planes; control means coupled to said error circuitry and said error logging store for testing the bit that is stored in the tag bit position of the one of said memory registers that is dedicated to the one of said bit planes to which the generated error word that is generated by said error circuitry is associated, said control means generating an error signal only if said test indicates that an error has not previously occurred in the associated one of said bit planes; said control means storing said generated error word in its associated one of said memory registers of said error logging store only if said test indicates that an error has not previously occurred in the associated one of said bit planes; defective device counter means responsively coupled to said control means for incrementing its count only upon the generation of said error signal; display means responsively coupled to said defective device counter means for monitoring said error signals.
Claim 8
Dependent Claim
299 words
In a data processing system that includes a memory system that is configured into N bit planes and B bits per bit plane, each bit plane being a replaceable component upon the detection of a single defective device or bit therein that provides an error upon readout, and error circuitry coupled to said memory system for generating, upon the detection of each of said errors in said memory system, an error word that is associated with only the one bit plane in which the error is detected, said error word comprising a single tag bit, said tag bit indicating that an error has occurred in said one bit plane, the improvement comprising: an error logging store comprised of a plurality of memory registers each memory register dedicated to represent only an associated different one of said bit planes; control means coupled to said error circuitry and said error logging store for testing the bit that is stored in the tag bit position of the one of said memory registers that is dedicated to the one of said bit planes to which the generated error word that is generated by said error circuitry is associated, said control means generating an error signal only if said test indicates that an error has not previously occurred in the associated one of said bit planes; said control means storing said generated error word in its associated one of said memory registers of said error logging store only if said test indicates that an error has not previously occurred in the associated one of said bit planes; defective device counter means responsively coupled to said control means for incrementing its count only upon the generation of said error signal; display means responsively coupled to said defective device counter means for monitoring said error signals.
Claim 9
Dependent Claim
366 words
In a data processing system that includes an LSI semiconductor memory system that is configured into M word groups of N bit planes per word group and B bits per bit plane, each bit plane being a replaceable component upon the detection of a single defective device or bit therein that provides a correctable error upon readout and single error correction circuitry coupled to said memory system for generating uPon the detection of each correctable error in said memory system a generated error word that is associated with the one of M word groups in which the correctable error is detected, said generated error word comprising a single tag bit and a plurality of syndrome bits, said tag bit indicating that a correctable error has occurred in said one of M word groups in the one bit plane that is identified by said syndrome bits, the improvement comprising: an error logging store comprised of M memory registers, each memory register dedicated to represent only an associated different one of said M word groups; control means responsively coupled to said single error correction circuitry and said error logging store for comparing the tag bit of the generated error word to the bit that is stored in the tag bit position of the one of the M memory registers that is dedicated to the one of the M word groups to which the generated error word is associated, said control means generating a defective device count only if said comparison indicates that a correctable error has not previously occurred in the associated one of said M word groups; said control means transferring said generated error word from said single error correction circuitry to said error logging store for storing it in its associated one of said M memory registers of said error logging store only if said comparison indicates that a correctable error has not previously occurred in the associated one of said M word groups; defective device counter means responsively coupled to said control means for incrementing its count only upon the generation of each of said defective device counts; and, display means responsively coupled to said defective device counter means for monitoring said defective device count.
Claim 10
Dependent Claim
366 words
In a data processing system that includes an LSI semiconductor memory system that is configured into M word groups of N bit planes per word group and B bits per bit plane, each bit plane being a replaceable component upon the detection of a single defective device or bit therein that provides a correctable error upon readout and single error correction circuitry coupled to said memory system for generating uPon the detection of each correctable error in said memory system a generated error word that is associated with the one of M word groups in which the correctable error is detected, said generated error word comprising a single tag bit and a plurality of syndrome bits, said tag bit indicating that a correctable error has occurred in said one of M word groups in the one bit plane that is identified by said syndrome bits, the improvement comprising: an error logging store comprised of M memory registers, each memory register dedicated to represent only an associated different one of said M word groups; control means responsively coupled to said single error correction circuitry and said error logging store for comparing the tag bit of the generated error word to the bit that is stored in the tag bit position of the one of the M memory registers that is dedicated to the one of the M word groups to which the generated error word is associated, said control means generating a defective device count only if said comparison indicates that a correctable error has not previously occurred in the associated one of said M word groups; said control means transferring said generated error word from said single error correction circuitry to said error logging store for storing it in its associated one of said M memory registers of said error logging store only if said comparison indicates that a correctable error has not previously occurred in the associated one of said M word groups; defective device counter means responsively coupled to said control means for incrementing its count only upon the generation of each of said defective device counts; and, display means responsively coupled to said defective device counter means for monitoring said defective device count.
Claim 11
Dependent Claim
357 words
In a data processing system that includes an LSI semiconductor memory system that is configured into M word groups of N bit planes per word group and B bits per bit plane, each bit plane being a replaceable component upon the detection of a single defective device or bit therein that provides a correctable error upon readout and single error correction circuitry coupled to said memory system for generating upon the detection of each correctable error in said memory system a generated error word that is associated with the one of M word groups in which the correctable error is detected, said generated error word comprising a single tag bit and a plurality of syndrome bits, said tag bit indicating that a correctable error has occurred in said one of M word groups in the one bit plane that is identified by said syndrome bits, the improvement comprising: an error logging store comprised of M memory registers, each memory register dedicated to represent only an associated different one of said M word groups; control means responsively coupled to said single error correction circuitry and said error logging store for testing the bit that is stored in the tag bit position of the one of the M memory registers that is dedicated to the one of the M word groups to which the generated error word is associated, said control means generating a defective device count only if said test indicates that a correctable error has not previously occurred in the associated one of said M word groups; said control means transferring said generated error word from said single error correction circuitry to said error logging store for storing it in its associated one of said M memory registers of said error logging store only if said test indicates that a correctable error has not previously occurred in the associated one of said M word groups; defective device counter means responsively coupled to said control means for incrementing its count only upon the generation of each of said defective device counts; and, display means responsively coupled to said defective device counter means for monitoring said defective device count.
Claim 12
Dependent Claim
357 words
In a data processing system that includes an LSI semiconductor memory system that is configured into M word groups of N bit planes per word group and B bits per bit plane, each bit plane being a replaceable component upon the detection of a single defective device or bit therein that provides a correctable error upon readout and single error correction circuitry coupled to said memory system for generating upon the detection of each correctable error in said memory system a generated error word that is associated with the one of M word groups in which the correctable error is detected, said generated error word comprising a single tag bit and a plurality of syndrome bits, said tag bit indicating that a correctable error has occurred in said one of M word groups in the one bit plane that is identified by said syndrome bits, the improvement comprising: an error logging store comprised of M memory registers, each memory register dedicated to represent only an associated different one of said M word groups; control means responsively coupled to said single error correction circuitry and said error logging store for testing the bit that is stored in the tag bit position of the one of the M memory registers that is dedicated to the one of the M word groups to which the generated error word is associated, said control means generating a defective device count only if said test indicates that a correctable error has not previously occurred in the associated one of said M word groups; said control means transferring said generated error word from said single error correction circuitry to said error logging store for storing it in its associated one of said M memory registers of said error logging store only if said test indicates that a correctable error has not previously occurred in the associated one of said M word groups; defective device counter means responsively coupled to said control means for incrementing its count only upon the generation of each of said defective device counts; and, display means responsively coupled to said defective device counter means for monitoring said defective device count.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-09-15 | 1979-03-17 | 1979-09-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-09-15 | 1983-03-17 | 1983-09-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-09-15 | 1987-03-17 | 1987-09-16 | $7700.00 | Window Closed / Lapsed |