Threshold logic using complementary mos device

Claim 2

A majority logic gate for indicating when the sum of the integer weights of any one of a plurality of selected combinations of a multiplicity of weighted input signals is greater than half the sum of the weights of all of the input signals, said sum of the weights of all of the input signals being an odd integer comprising, in combination: first, second and output terminals; a first network having a plurality of parallel-connected circuits, each of said first network circuits having a plurality of source-to-drain series-connected first network MOS devices of a first channel conductivity type, each of said first network MOS devices having a gate for receiving a respective one of said input signals associated with a respective one of said selected combinations, the source of the first MOS device in each of said first network circuits commonly connected to said first terminal and the drain of the last MOS device in each of said first network circuits commonly connected to said output terminal; and a second network having a plurality of parallel-connected circuits, each of said second network circuits having a plurality of source-to-drain series-connected second network MOS devices of a second channel conductivity type opposite to said first channel conductivity type, each of said second network MOS devices having a gate for receiving a respective one of said input signals associated with a respective one of said selected combinations, the source of tHe first of said second network MOS device in each of said second network circuits commonly connected to said second terminal and the drain of the last MOS device in each of said second network circuits commonly connected to said output terminal; whereby said first and second networks for a complementary MOS circuit.

Claim 3

A logic gate according to claim 1 wherein said first network MOS devices are of P type material and said second network MOS devices are of N type material.

Claim 4

A gate circuit according to claim 2 wherein said first terminal is connected to a first voltage source and said second terminal is connected to a second voltage source.

Claim 5

A logic gate according to claim 3 wherein said first voltage source has a more positive potential than said second voltage source.

Claim 6

A gate circuit according to claim 1 wherein said series connected MOS devices provide an AND logic function.

Claim 7

A gate circuit according to claim 1 wherein the common connections of said first and last MOS devices in each circuit provide a NOR logic function.

Claim 8

A majority logic gate for indicating the occurrence of any one of three selected combinations X1X2, X1X3, X2X3, drawn from three unity-weighted input signals X1, X2, X3, comprising, in combination: first, second and output terminals; a first network having first, second, third, fourth and fifth P-channel MOS devices, said first P-channel device including a gate for receiving input signal X2, a source connected to said first terminal and a drain, said second P-channel device including a gate for receiving input signal X3, a source connected to said drain of said first P-channel device and a drain connected to said output terminal, said third P-channel device including a gate for receiving input signal X2, a source connected to said first terminal and a drain, said fourth P-channel device including a gate for receiving input signal X3, a source connected to said first terminal and a drain connected to said drain of said third P-channel device, said fifth P-channel device including a gate for receiving input signal X1, a source commonly connected to said drains of said third and fourth P-channel devices and a drain connected to said output terminal; and a second network having first, second, third, fourth and fifth N-channel MOS devices, said first N channel device including a gate for receiving input signal X2, a drain connected to said output terminal and a source, said second N-channel device including a gate for receiving input signal X3, a drain connected to said source of said first N-channel device and a source connected to said second terminal, said third N-channel device including a gate for receiving input signal X2, a drain connected to said output terminal and a source, said fourth N-channel device including a gate for receiving input signal X3, a drain connected to said output terminal and a source connected to said source of said third N-channel device, said fifth N-channel device including a gate for receiving input signal X1, a drain commonly connected to said sources of said third and fourth N-channel devices, and a source connected to said second terminal; whereby said first and second networks form a complementary MOS circuit.

Claim 9

A majority logic gate for indicating the occurrence of any one of three selected combinations X1X2, X1X3, X2X3, drawn from three unity-weighted input signals X1, X2, X3, comprising, in combination: first, second and output terminals; a first network having first, second, third, fourth and fifth P-channel MOS devices, said first P-channel device including a gate for receiving input signal X2, a source connected to said first terminal and a drain, said second P-channel device including a gate for receiving input signal X3, a source connected to said drain of said first P-channel device and a drain connected to said output terminal, said third P-channel device including a gate for receiving input signal X2, a source connected to said first terminal and a drain, said fourth P-channel device including a gate for receiving input signal X3, a source connected to said first terminal and a drain connected to said drain of said third P-channel device, said fifth P-channel device including a gate for receiving input signal X1, a source commonly connected to said drains of said third and fourth P-channel devices and a drain connected to said output terminal; and a second network having first, second, third, fourth and fifth N-channel MOS devices, said first N channel device including a gate for receiving input signal X2, a drain connected to said output terminal and a source, said second N-channel device including a gate for receiving input signal X3, a drain connected to said source of said first N-channel device and a source connected to said second terminal, said third N-channel device including a gate for receiving input signal X2, a drain connected to said output terminal and a source, said fourth N-channel device including a gate for receiving input signal X3, a drain connected to said output terminal and a source connected to said source of said third N-channel device, said fifth N-channel device including a gate for receiving input signal X1, a drain commonly connected to said sources of said third and fourth N-channel devices, and a source connected to said second terminal; whereby said first and second networks form a complementary MOS circuit.