Redundant signal processing error reduction technique

Claim 2

In combination: first means adapted for connection to a source of information signals; first and second channels connected to said first means, each of said channels having a signal storage means; second means for loading a first block of said information signals into said first channel signal storage means at a first clock rate; third means for reading out said first block of information signals from said first channel signal storage means and for re-loading said first block of signals into said first channel signal storage means and for subsequently reading out said reloaded first block of signals from said first channel signal storage means at a second clock rate higher than said first clock rate; fourth means for loading a second block of said information signals into said second channel signal storage means at said first clock rate during the time interval corresponding to the operation of said third means; fifth means for reading out said second block of information signals from said second channel signal storage means and for re-loading said second block of information signals into said second channel signal storage means and for subsequently reading out said re-loaded second block of information signals from said second channel signal storage means at said second clock rate at times corresponding to the loading of said first channel signal storage means at said first clock rate; and switch means connected to said first and second channels operable for providing at a given terminal, in a serial stream of signals, first and second representations of said first block of information signals from said fIrst channel and first and second representations of said second block of information signals from said second channel.

Claim 3

The apparatus according to claim 1 wherein said information signals and said signals representing said first and second blocks of information signals comprise digital signals and wherein said first and second channel signal storage means comprise shift registers.

Claim 4

The apparatus according to claim 2 further comprising: preamble generator means for providing a first particular digital signal and a second particular digital signal; first gating means for inserting said first particular digital signal in said first channel in a time interval just preceding the reading out of said initially loaded first block of information signals from said first channel shift register and for inserting said second particular digital signal in said first channel in a time interval just preceding the reading out of said re-loaded first block of information signals from said first channel shift register; and second gating means for inserting said first particular digital signal in said second channel in a time interval just preceding the reading out of said initially loaded second block of information signals from said second channel shift register and for inserting said second particular digital signal in said second channel in a time interval just preceding the reading out of said re-loaded second block of information signals from said second channel shift register.

Claim 5

The apparatus according to claim 3 further comprising: first parity means coupled to said first gating means for inserting a first digital parity bit in predetermined locations in said initially loaded first block of information signals and in said re-loaded first block of information signals read out of said first channel shift register; and second parity means coupled to said second gating means for inserting a second digital parity bit in predetermined locations in said initially loaded second block of information signals and in said re-loaded second block of information signals read out of said second channel shift register.

Claim 6

The apparatus according to claim 4 wherein said switch means comprises electronic gating circuits for alternately providing to said given terminal said first and second representations of said first block of information signals and then said first and second representations of said second block of information signals.

Claim 7

The apparatus according to claim 5 further comprising: a single track recorder for sequentially recording said representations, in the order named, in a single track on a record medium; and playback apparatus responsive to the representations of said information signals recorded on said single track of said record medium for detecting errors in said representations and for providing at a playback output terminal one substantially error-free representation of said first block of information signals and one substantially error-free representation of said second block of information signals.

Claim 8

The apparatus according to claim 6 wherein said playback apparatus further comprises: means responsive to the representations of said information signals recorded on said single track of said record medium for extracting a clock signal; and preamble detector means responsive to the representations of said information signals recorded on said single track of said record medium for detecting and providing indications of said first and second particular digital signals.

Claim 9

The apparatus according to claim 7 wherein said playback apparatus further comprises: a first playback channel, having at least one playback shift register, responsive to said first and second representations of said first block of information signals from the single track of said record medium and to said preamble detector means for loading said first representation of said first block of information signals into said first playback Channel shift register at the rate of said extracted clock signal and for providing said second representation of said first block of information signals at an intermediate terminal thereof; first channel error detecting means in said first playback channel responsive to said first playback channel shift register for detecting errors in said first representation of said first block of information signals; first channel switching means responsive to said first channel error detecting means for passing said first representation of said first block of information signals when said first representation thereof is error free and for switching to and passing at least a portion of said second representation thereof when an error is detected in the corresponding portion of said first representation thereof; a second playback channel having at least one playback shift register, responsive to said first and second representations of said second block of information signals from the single track of said record medium and to said preamble detector means for loading said first representation of said second block of information signals into said second channel playback shift register at the rate of said extracted clock signal and for providing said second representation of said second block of information signals at an intermediate terminal thereof; second channel error detecting means in said second playback channel responsive to said second playback channel shift register for detecting errors in said first representation of said first block of information signals; and second channel switching means responsive to said second channel error detecting means for passing said first representation of said second block of information signals when said first representation thereof is error free and for switching to and passing at least a portion of said second representation thereof when an error is detected in the corresponding portion of said first representation of said second block of information signals.

Claim 10

The apparatus according to claim 8 wherein said first and second playback channels further comprise another shift register in each of said channels responsive to the corresponding channel switching means and operating at a clock rate derived from and lower in frequency than the rate of said extracted clock signal.

Claim 11

The apparatus according to claim 9 further comprising output switching means having first and second input terminals connected respectively to said other shift register in each of said playback channels and operable to provide one substantially error-free representation of said first block of information signals from the first playback channel and, subsequently, one substantially error-free representation of said second block of information signals from said second playback channel to said playback apparatus output terminal.