US3882403A
Expired / Lapsed
US
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Digital frequency synthesizer
Assignee: General Dynamics Corp
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Filing: 1974-03-14
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Granted: 1975-05-06
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Expires: 1994-03-14
Abstract
Abstract A digital frequency synthesizer is described which employs an accumulator to determine the number of cycles of a reference frequency source which is divisible into the period of the frequency to be generated and to determine a digital number which is related to the remainder or the fractional cycle of the reference frequency required to complete the period of the generated frequency. A digital/analog interpolator translates this digital number into a fractional period and combines it with the integral determined by the accumulator division and outputs a pulse train having the combined period of the frequency to be synthesized.
Inventors
- 👤 William G Gerken
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 16:36
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/099; H03L7/0991; H03L7/0994
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
154 words
A frequency synthesizer which comprises a. means for providing a reference frequency signal; b. means for detecting the number of periods of said reference frequency signal equal to the lowest integral multiple of a number which is a factor of the frequency to be synthesized, which exceeds a certain number; c. means operated by said detecting means for providing upon detection of said number of periods, a signal which changes in amplitude; d. means also operated by said detecting means upon the detection of said number of periods for providing a signal level proportional to the difference between said lowest integral multiple and said certain number divided by said number which is a factor of the frequency to be synthesized; e. means for generating an output when said signal which changes in amplitude and said level are equal to each other; and f. said output providing the signal having the frequency to be synthesized.
Claim 2
Dependent Claim
154 words
A frequency synthesizer which comprises a. means for providing a reference frequency signal; b. means for detecting the number of periods of said reference frequency signal equal to the lowest integral multiple of a number which is a factor of the frequency to be synthesized, which exceeds a certain number; c. means operated by said detecting means for providing upon detection of said number of periods, a signal which changes in amplitude; d. means also operated by said detecting means upon the detection of said number of periods for providing a signal level proportional to the difference between said lowest integral multiple and said certain number divided by said number which is a factor of the frequency to be synthesized; e. means for generating an output when said signal which changes in amplitude and said level are equal to each other; and f. said output providing the signal having the frequency to be synthesized.
Claim 3
Dependent Claim
21 words
The invention as set forth in claim 1, further comprising means controlled by said output for providing the frequency synthesized signal.
Claim 4
Dependent Claim
24 words
The invention as set forth in claim 2 wherein said output controlled means is a phase locked loop which is locked to said output.
Claim 5
Dependent Claim
51 words
The invention as set forth in claim 1 wherein said certain number of 2N, said number which is a factor of the frequency to be synthesized is K, and said number of periods is P, said detecting means being operative to detect said lowest integral multiple n, when nK > P(2N).
Claim 6
Dependent Claim
25 words
The invention as set forth in claim 4 wherein said means for providing said signal level includes means operative to provide a number equal to
Claim 7
Dependent Claim
45 words
The invention as set forth in claim 5 wherein said means which provides said signal which changes in amplitude is operative to provide said signal which, as a function of time, has a form similar to the number provided by said signal level providing means.
Claim 8
Dependent Claim
32 words
The invention as set forth in claim 6 wherein the forM of said signal which changes in amplitude is (1 - R) where R has a value proportional to nK - P(2N).
Claim 9
Dependent Claim
57 words
The invention as set forth in claim 1 wherein said detecting means comprises an accumulator having storage for said certain number, means for successively incrementing said accumulator during each period of said reference frequency signal by said number which is said factor of said frequency to be synthesized, and means for detecting an overflow from said accumulator.
Claim 10
Dependent Claim
35 words
The invention as set forth in claim 8 wherein said incrementing means comprises a register, and means for programming said register to store said number which is said factor of said frequency to be synthesized.
Claim 11
Dependent Claim
53 words
The invention as set forth in claim 9 wherein said programming means comprises a plurality of switches each for a different decimal digit of the frequency to be synthesized, each of said switches having BCD outputs connected to said register for setting said register to store a binary number corresponding to said frequency.
Claim 12
Dependent Claim
19 words
The invention as set forth in claim 8 wherein said accumulator has N stages, 2N being said certain number.
Claim 13
Dependent Claim
21 words
The invention as set forth in claim 11 wherein 2N is equal or greater than the highest frequency to be synthesized.
Claim 14
Dependent Claim
18 words
The invention as set forth in claim 12 wherein said reference frequency is greater than said highest frequency.
Claim 15
Dependent Claim
22 words
The invention as set forth in claim 13 wherein said reference frequency is at least ten times greater than said highest frequency.
Claim 16
Dependent Claim
72 words
The invention as set forth in claim 8 wherein said signal level providing means comprises a divider, means operative by said overflow detecting means for transferring the number stored in said accumulator to the dividend input of said divider, means for transferring the number stored in said register to the divisor input of said divider, and means for converting the number provided at the quotient output of said divider into said level.
Claim 17
Dependent Claim
18 words
The invention as set forth in claim 15 wherein said converting means is a digital to analog converter.
Claim 18
Dependent Claim
45 words
The invention as set forth in claim 16 further comprising means operated by said overflow detecting means for providing a first output a certain time after each overflow is detected, and means for enabling said digital to analog converter upon occurrence of said first output.
Claim 19
Dependent Claim
61 words
The invention as set forth in claim 17 wherein said means for providing said signal which changes in amplitude is a negative ramp generator which provides ramp voltage of linearly decreasing amplitude, and means operated by said overflow detecting means for initiating said ramp voltage a certain time after said digital to analog converter is enabled to provide said signal level.
Claim 20
Dependent Claim
18 words
The invention as set forth in claim 18 wherein said means for generating said output comprises a comparator.
Claim 21
Dependent Claim
38 words
The invention as set forth in claim 19 further comprising a phase locked loop including a voltage controlled oscillator, which provides said synthesized signal and means for applying said output to said loop for locking said oscillator thereto.
Claim 22
Dependent Claim
45 words
The invention as set forth in claim 20 further comprising a digital to analog converter having its digital inputs connected to said register and its analog output connected to said oscillator for coarse tuning said oscillation to the frequency of the signal to be synthesized.
Claim 23
Dependent Claim
39 words
The invention as set forth in claim 20 wherein said factor is an integral submultiple of said frequency to be synthesized and said oscillator is tuned to a frequency which is multiplied by the reciprocal of said integral submultiple.
References Cited (Backward Citations)
US3651422A
Cited
US3689849A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-05-05 | 1978-11-04 | 1979-05-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-05-05 | 1982-11-04 | 1983-05-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-05-05 | 1986-11-04 | 1987-05-06 | $7700.00 | Window Closed / Lapsed |