US3879710A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Data processor for a loop data communications system
Assignee: RCA Corp
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Filing: 1974-03-01
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Granted: 1975-04-22
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Expires: 1994-03-01
Abstract
Abstract A data processor for a time division multiplexed communications system. A plurality of such data processors are connected in series in a loop configuration, each having a data terminal associated therewith, for establishing a connection between data processors in a time division multiplexed channel. Each data processor demodulates the signal on the loop, extracts timing information from the loop signal and locates the channel to be used for establishing the connection between itself and another data processor. Each data processor in addition, regenerates and passes on data not intended for that data processor. Data found in the correct or selected channel is provided to the data terminal which may be a synchronous or an asynchronous device. Data from the terminal is inserted into the selected channel, modulated in accordance with a particular rule and transmitted onto the loop to another data processor operating in the selected channel.
Inventors
- 👤 Nicholad Frank Maxemchuk
- 👤 Hugh Edward White
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-22 20:09
CPC Classifications
H; H04; H04L; H04L12/00; H04L12/28; H04L12/42; H04L12/427; H04L12/43; G; G06; G06F; G06F13/00; G06F13/38; G06F13/42; G06F13/4247; H04L25/00; H04L25/02; H04L25/20; H04L25/24; H04L25/242
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
363 words
A given data processor for a time division multiplexed communications system, wherein a plurality of data processors are connected in series in a loop configuration, each of said data processors being associated with a data terminal, each of said data processors further having a calling and a called mode of operation for transmitting and receiving digital information signals to and from said loop in a selected time division multiplexed channel within a frame of channels, said frame comprising a plurality of sub-frames, each sub-frame being preceded by a digital address signal, each channel comprising at least a first and a second time slot, said given data processor comprising: first means adapted to receive said digital information signals from said loop; channel identification means connected to said first means and responsive to said digital address signals for locating said first and second time slots of said selected time division multiplexed channel; second means for inserting digital data signals onto said loop from the associated data terminal in said second time slot of said selected channel when said given data processor is in said calling mode of operation and for inserting digital data signals onto said loop from said associated data terminal in said first time slot of said selected channel when said given data processor is in said called mode of operation; third means for inserting a digital connection signal, indicative of the status of a connection between said given data processor and another data processor on said loop, in said first time slot of said selected channel when said given data processor is in said calling mode of operation and for inserting said digital connection signal in said second time slot of said selected channel when said given data processor is in said called mode of operation; and busy indication means coupled to said channel identification means for analyzing said first and second time slots of said selected channel and for detecting the presence of said digital connection signal from another data processor, said busy indication means preventing access to said selected channel by said given data processor when a digital connection signal is detected in said first or said second time slot.
Claim 2
Dependent Claim
363 words
A given data processor for a time division multiplexed communications system, wherein a plurality of data processors are connected in series in a loop configuration, each of said data processors being associated with a data terminal, each of said data processors further having a calling and a called mode of operation for transmitting and receiving digital information signals to and from said loop in a selected time division multiplexed channel within a frame of channels, said frame comprising a plurality of sub-frames, each sub-frame being preceded by a digital address signal, each channel comprising at least a first and a second time slot, said given data processor comprising: first means adapted to receive said digital information signals from said loop; channel identification means connected to said first means and responsive to said digital address signals for locating said first and second time slots of said selected time division multiplexed channel; second means for inserting digital data signals onto said loop from the associated data terminal in said second time slot of said selected channel when said given data processor is in said calling mode of operation and for inserting digital data signals onto said loop from said associated data terminal in said first time slot of said selected channel when said given data processor is in said called mode of operation; third means for inserting a digital connection signal, indicative of the status of a connection between said given data processor and another data processor on said loop, in said first time slot of said selected channel when said given data processor is in said calling mode of operation and for inserting said digital connection signal in said second time slot of said selected channel when said given data processor is in said called mode of operation; and busy indication means coupled to said channel identification means for analyzing said first and second time slots of said selected channel and for detecting the presence of said digital connection signal from another data processor, said busy indication means preventing access to said selected channel by said given data processor when a digital connection signal is detected in said first or said second time slot.
Claim 3
Dependent Claim
363 words
A given data processor for a time division multiplexed communications system, wherein a plurality of data processors are connected in series in a loop configuration, each of said data processors being associated with a data terminal, each of said data processors further having a calling and a called mode of operation for transmitting and receiving digital information signals to and from said loop in a selected time division multiplexed channel within a frame of channels, said frame comprising a plurality of sub-frames, each sub-frame being preceded by a digital address signal, each channel comprising at least a first and a second time slot, said given data processor comprising: first means adapted to receive said digital information signals from said loop; channel identification means connected to said first means and responsive to said digital address signals for locating said first and second time slots of said selected time division multiplexed channel; second means for inserting digital data signals onto said loop from the associated data terminal in said second time slot of said selected channel when said given data processor is in said calling mode of operation and for inserting digital data signals onto said loop from said associated data terminal in said first time slot of said selected channel when said given data processor is in said called mode of operation; third means for inserting a digital connection signal, indicative of the status of a connection between said given data processor and another data processor on said loop, in said first time slot of said selected channel when said given data processor is in said calling mode of operation and for inserting said digital connection signal in said second time slot of said selected channel when said given data processor is in said called mode of operation; and busy indication means coupled to said channel identification means for analyzing said first and second time slots of said selected channel and for detecting the presence of said digital connection signal from another data processor, said busy indication means preventing access to said selected channel by said given data processor when a digital connection signal is detected in said first or said second time slot.
Claim 4
Dependent Claim
363 words
A given data processor for a time division multiplexed communications system, wherein a plurality of data processors are connected in series in a loop configuration, each of said data processors being associated with a data terminal, each of said data processors further having a calling and a called mode of operation for transmitting and receiving digital information signals to and from said loop in a selected time division multiplexed channel within a frame of channels, said frame comprising a plurality of sub-frames, each sub-frame being preceded by a digital address signal, each channel comprising at least a first and a second time slot, said given data processor comprising: first means adapted to receive said digital information signals from said loop; channel identification means connected to said first means and responsive to said digital address signals for locating said first and second time slots of said selected time division multiplexed channel; second means for inserting digital data signals onto said loop from the associated data terminal in said second time slot of said selected channel when said given data processor is in said calling mode of operation and for inserting digital data signals onto said loop from said associated data terminal in said first time slot of said selected channel when said given data processor is in said called mode of operation; third means for inserting a digital connection signal, indicative of the status of a connection between said given data processor and another data processor on said loop, in said first time slot of said selected channel when said given data processor is in said calling mode of operation and for inserting said digital connection signal in said second time slot of said selected channel when said given data processor is in said called mode of operation; and busy indication means coupled to said channel identification means for analyzing said first and second time slots of said selected channel and for detecting the presence of said digital connection signal from another data processor, said busy indication means preventing access to said selected channel by said given data processor when a digital connection signal is detected in said first or said second time slot.
Claim 5
Dependent Claim
71 words
The given data processor according to claim 1 further comprising modulation means for translating digital signals provided by said associated data terminal from a first format to a second format, said second format having a first sequence of voltage levels to represent a logical one and a second sequence of voltage levels to represent a logical zero, said first and second sequences having an average D. C. level of zero volts.
Claim 6
Dependent Claim
48 words
The given data processOr according to claim 2 further comprising demodulation means for translating digital information signals received from said loop in said second format to said first format, said first format having one voltage level representing a logical one and another voltage level representing a logical zero.
Claim 7
Dependent Claim
40 words
The data processor according to claim 3 wherein said channel identification means comprises a slot counter responsive to said digital address signals for counting down said time division multiplexed time slots to said selected channel first and second time slots.
Claim 8
Dependent Claim
74 words
The given data processor according to claim 4 further comprising: timing extraction means coupled to said first means for deriving at least one clock signal from said received digital information signals; clock counter means responsive to said at least one clock signal for providing a plurality of timing information signals; and means for coupling a selected one of said plurality of timing information signals to the data terminal associated with said given data processor.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-04-21 | 1978-10-21 | 1979-04-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-04-21 | 1982-10-21 | 1983-04-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-04-21 | 1986-10-21 | 1987-04-22 | $7700.00 | Window Closed / Lapsed |