Data processor for multistation photometers

Claim 1

In a rotary photometric analyzer device including a plurality of cuvettes positioned in the rotor of said device with each of said cuvettes containing a respective sample to be analyzed, said rotor adapted to provide a rotor pulse for each complete revolution of said rotor and a digitized pulse for each cuvette position of said rotor during rotation thereof, and a photomultiplier tube positioned to receive respective transmittance values of the amount of light transmitted through each of said cuvettes as the rotor of said device is rotated, said tube providing a plurality of sequential output signals therefrom as a function of said transmittance values, the improvement comprising a digital logic system coupled to the output of said photomultiplier tube for processing said output signals received therefrom, said logic system comprising a log converter coupled to the output of said photomultiplier tube, a bipolar scratch pad memory unit, an analog-to-digital converter coupled between the output of said log converter and the input to said memory unit to provide digital signals for sequential storage into said memory unit, a print switch, a first flipflop coupled to said print switch, a timer coupled through a first gate to said first flipflop for enablement thereof, a second flipflop and a third flipflop coupled to the output of said first flipflop, a first pulse shaper for receiving said rotor pulse from said rotor and providing a common clock pulse to said second and third flipflops, a second pulse shaper for receiving said digitized pulses from said cuvette rotor positions, a second gate coupled between said second pulse shaper and said analog-todigital converter, said second pulse shaper providing gating pulses to said second gate which in turn triggers said converter, a fourth flipflop coupled between said analog-to-digital converter and said memory unit, a binary counter coupled by means of a third gate to the output of said fourth flipflop, the output of said counter coupled to said memory unit to provide the address advance thereto, a fourth gate coupled to the output of said third flipflop, the output of said fourth gate coupled to said second gate for providing a qualifying input thereto, whereby when said print switch is closed and a first rotor pulse is received said digital signals are sequentially stored in said memory unit and said counter is sequentially advanced and upon recipt of a second rotor pulse said counter is reset by means of a fifth gate coupled to the output of said fourth gate while at the same time said fourth gate effects disablement of said second gate, said system further including a printer, an inverter coupled to the output of said memory unit, and a binary-to-binary coded decimal converter coupled between said inverter and said printer, a sixth gate, a fifth flipflop, and a divide-by-thirty counter, said sixth gate coupled to the output of said first pulse shaper and to the output of said third flipflop, said fifth flipflop coupled to the output of said sixth gate and to the output of said first gate, the output of said fifth flipflop coupled to said divide-by-thirty counter, said last-named counter coupled by means of said third gate to said binary counter to again sequentially advance it, said last-named counter also coupled to said printer to provide successive print signals thereto, whereby upon receipt of a third rotor pulse by first pulse shaper said signals stored in said memory unit are sequentially read out therefrom and printed by said printer, after which said system is restored to its initial condition by means of a final signal from said binary counter to said first gate.