Programmable logic controller

Claim 2

A programmable logic controller for controlling a device having at least one input and at least one output comprising: main memory means for storing a plurality of programs, each of said plurality of programs consisting of a sequence of instructions, each instruction comprising an output part, an input part and two destination address parts; auxiliary memory means for storing a plurality of program addresses corresponding to said plurality of programs; program select register means operatively connected to said auxiliary memory means for selecting one of said plurality of program addresses stored in said auxiliary memory means; address reading means operatively connected to said auxiliary memory means for reading out the program address in said auxiliary memory means selected by said program select register means; memory address register means operatively connected to said main memory means and to said auxiliary memory means for addressing said main memory means with said program address read out by said address reading means; instruction reading means operatively connected to said main memory means for reading out the instruction in said main memory means addressed by said memory address register means; instruction register means operatively connected to said main memory means for storing said instruction read out by said instruction reading means; input and output control circuit means operatively connected to said instruction register means and to said device and having a plurality of input terminals to which said at least one input of said device is connected and a plurality of output terminals to which said at least one output of said device is connected, said input and output control circuit means including a decoder means operatively connected to said instruction register means for selecting one of said plurality of output terminals specified by said output part of said instruction stored in said instruction register means, means operatively connected to said decoder means for energizing and deenergizing the output connected to the output terminal selected by said decoder means in accordance with said output part of said instruction stored in said instruction-register means, a second decoder means operatively connected to said instruction register means for selecting one of said plurality of input terminals specified by said input part of said instruction stored in said instruction register means, comparing means operatively connected to said second decoder means for comparing the input connected to the input terminal selected by said second decoder means with the condition specified by said input part of said instruction stored in said instruction register means, and selecting means, connected to said comparing means and responsive to the result of the comparison for selecting one of two destination address parts of said instruction in said instruction register means depending upon said result of said comparison; destination address reading means operatively connected to said instruction register means and to said selecting means for reading out the destination address part of said instruction stored in said instruction register means selected by said selecting means; temporary register means operatively connected to said instruction register means for storing said destination address part read out by said destination address reading means; writing means operatively connected to said auxiliary memory means for writing said destination address part in said temporary register means into the same location of said auxiliary memory means from which said program address was read out by said address reading means; and means operatively connected to said program select register means for causing said program select register means to select a different program Address after said destination address is written into said auxiliary memory means by said writing means.

Claim 3

A programmable logic controller for controlling a plurality of devices each of said plurality of devices having at least one input and at least one output comprising: main memory means for storing a plurality of programs, each of said plurality of programs consisting of a sequence of instructions, each instruction comprising an output part, an input part and two destination address parts; auxiliary memory means for storing a plurality of sets of program addresses corresponding to said plurality of devices, each of said sets, of program addresses corresponding to said plurality of programs stored in said main memory means; program select register means operatively connected to said auxiliary memory means for selecting one program address of said plurality of sets of program addresses stored in said auxiliary memory means; address reading means operatively connected to said auxiliary memory means for reading out the program address in said auxiliary memory means selected by said program select register means; memory address register means operatively connected to said main memory means and to said auxiliary memory means with said program address read out by said address reading means; instruction reading means operatively connected to said main memory means for reading out the instruction in said main memory means addressed by said memory address register means; instruction register means operatively connected to said main memory means for storing said instruction read out by said instruction reading means; a plurality of input and output control circuit means of operatively connected to said instruction register means and to said plurality of devices, each having a plurality of input terminals to which said at least one input of each of said plurality of devices is connected and a plurality of output terminals to which said at least one output of each of said plurality of devices is connected, each of said plurality of input and output control means including a decoder means operatively connected to said instruction register means and to said program select register means for selecting one of said plurality of output terminals of each of said plurality of devices specified by said output part of said instruction in said instruction register means, said decoder means for each of said plurality of devices being selectively activated by said program select register means, means operatively connected to said decoder means for energizing and deenergizing the output connected to the output terminal selected by said decoder means in accordance with said output part of said instruction in said instruction register means, a second decoder means operatively connected to said instruction register means and to said program select register means for selecting one of said plurality of input terminals of each of said plurality of devices specified by said input part of said instruction in said instruction register means and comparing means operatively connected to said second decoder means for comparing the input connected to the input terminal selected by said second decoder means with the condition specified by said input part of said instructions in said instruction register means; selecting means connected to said comparing means and responsive to the result of the comparison for selecting one of two destination address parts of said instruction in said instruction register means depending upon said result of said comparison; destination address reading means operatively connected to said instruction register means and to said selecting means for reading out the destination address part in said instruction stored in said instruction register means selected by said selecting means; temporary register means operatively connected to said instruction register means for storing said destination address part read out by said desTination address reading means; writing means operatively connected to said auxiliary memory means for writing said destination address part in said temporary register means into the same location of said auxiliary memory means from which said program address was read out by said address reading means; and means operatively connected to said program select register means for causing said program select register means to select a different program address after said destination address is written into said auxiliary memory means by said writing means.

Claim 4

A programmable logic controller for controlling a plurality of devices each of said plurality of devices having at least one input and at least one output comprising: main memory means for storing a plurality of programs, each of said plurality of programs consisting of a sequence of instructions, each instruction comprising an output part, an input part and two destination address parts; auxiliary memory means for storing a plurality of sets of program addresses corresponding to said plurality of devices, each of said sets, of program addresses corresponding to said plurality of programs stored in said main memory means; program select register means operatively connected to said auxiliary memory means for selecting one program address of said plurality of sets of program addresses stored in said auxiliary memory means; address reading means operatively connected to said auxiliary memory means for reading out the program address in said auxiliary memory means selected by said program select register means; memory address register means operatively connected to said main memory means and to said auxiliary memory means with said program address read out by said address reading means; instruction reading means operatively connected to said main memory means for reading out the instruction in said main memory means addressed by said memory address register means; instruction register means operatively connected to said main memory means for storing said instruction read out by said instruction reading means; a plurality of input and output control circuit means of operatively connected to said instruction register means and to said plurality of devices, each having a plurality of input terminals to which said at least one input of each of said plurality of devices is connected and a plurality of output terminals to which said at least one output of each of said plurality of devices is connected, each of said plurality of input and output control means including a decoder means operatively connected to said instruction register means and to said program select register means for selecting one of said plurality of output terminals of each of said plurality of devices specified by said output part of said instruction in said instruction register means, said decoder means for each of said plurality of devices being selectively activated by said program select register means, means operatively connected to said decoder means for energizing and deenergizing the output connected to the output terminal selected by said decoder means in accordance with said output part of said instruction in said instruction register means, a second decoder means operatively connected to said instruction register means and to said program select register means for selecting one of said plurality of input terminals of each of said plurality of devices specified by said input part of said instruction in said instruction register means and comparing means operatively connected to said second decoder means for comparing the input connected to the input terminal selected by said second decoder means with the condition specified by said input part of said instructions in said instruction register means; selecting means connected to said comparing means and responsive to the result of the comparison for selecting one of two destination address parts of said instruction in said instruction register means depending upon said result of said comparison; destination address reading means operatively connected to said instruction register means and to said selecting means for reading out the destination address part in said instruction stored in said instruction register means selected by said selecting means; temporary register means operatively connected to said instruction register means for storing said destination address part read out by said desTination address reading means; writing means operatively connected to said auxiliary memory means for writing said destination address part in said temporary register means into the same location of said auxiliary memory means from which said program address was read out by said address reading means; and means operatively connected to said program select register means for causing said program select register means to select a different program address after said destination address is written into said auxiliary memory means by said writing means.

Claim 5

A programmable logic controller for controlling a device having at least one input and at least one output comprising: main memory means for storing a plurality of programs, each of said plurality of programs consisting of a sequence of instructions including input and output instructions and destination addresses; auxiliary memory means for storing a plurality of program addresses corresponding to said plurality of programs; program select register means operatively connected to said auxiliary memory means for selecting one of said plurality of program addresses stored in said auxiliary memory means; address reading means operatively connected to said auxiliary memory means for reading out the program address in said auxiliary memory means selected by said program select register means, memory address register means operatively connected to said main memory means and to said auxiliary memory means for addressing said main memory means with said program address read out by said address reading means; instruction reading means operatively connected to said main memory means for reading out the input and output instruction in said main memory means addressed by said memory address register means; instruction register means operatively connected to said main memory means for storing said input and output instruction read out by said instruction reading means; input and output control circuit means operatively connected to said instruction register means and to said device and having a plurality of input terminals to which said at least one input of said device is connected and a plurality of output terminals to which said at least one output of said device is connected, said input and output control circuit means including a decoder means operatively connected to said instruction register means for selecting one of said plurality of output terminals specified by an output instruction in said instruction register means, means operatively connected to said decoder means for energizing and deenergizing output connected to the output terminal selected by said decoder means in accordance with said output instruction in said instruction register means, a second decoder means operatively connected to said instruction register means for selecting one of said plurality of input terminals specified by an input instruction in said instruction register means, comparing means operatively connected to said second decoder means for comparing the input connected to the input terminal selected by said second decoder means with the condition specified by said input instruction in said instruction register means; address modifying means operatively connected to said memory address register means for modifying said program address in said memory address register means; destination address reading means operatively connected to said main memory means for reading out the destination address in said main memory means addressed by said memory address register means; temporary register means operatively connected to said main memory means for storing said destination address read out by said destination address reading means; writing means operatively connected to said auxiliary memory means for writing said destination address in said temporary register means into the same location of said auxiliary memory means from which said program address was read out by said address reading Means; means operatively connected to said program select register means for causing said program select register means to select a different program address after said destination address is written into said auxiliary memory means by said writing means: and program control means coupled to said comparing means and responsive to the result of the comparison by said comparing means for modifying said program address in said memory address register means so as to skip to read out said destination address in said main memory means only when said result of said comparison is satisfactory.

Claim 6

A programmable logic controller for controlling a device having at least one input and at least one output comprising: main memory means for storing a plurality of programs, each of said plurality of programs consisting of a sequence of instructions including input and output instructions and destination addresses; auxiliary memory means for storing a plurality of program addresses corresponding to said plurality of programs; program select register means operatively connected to said auxiliary memory means for selecting one of said plurality of program addresses stored in said auxiliary memory means; address reading means operatively connected to said auxiliary memory means for reading out the program address in said auxiliary memory means selected by said program select register means, memory address register means operatively connected to said main memory means and to said auxiliary memory means for addressing said main memory means with said program address read out by said address reading means; instruction reading means operatively connected to said main memory means for reading out the input and output instruction in said main memory means addressed by said memory address register means; instruction register means operatively connected to said main memory means for storing said input and output instruction read out by said instruction reading means; input and output control circuit means operatively connected to said instruction register means and to said device and having a plurality of input terminals to which said at least one input of said device is connected and a plurality of output terminals to which said at least one output of said device is connected, said input and output control circuit means including a decoder means operatively connected to said instruction register means for selecting one of said plurality of output terminals specified by an output instruction in said instruction register means, means operatively connected to said decoder means for energizing and deenergizing output connected to the output terminal selected by said decoder means in accordance with said output instruction in said instruction register means, a second decoder means operatively connected to said instruction register means for selecting one of said plurality of input terminals specified by an input instruction in said instruction register means, comparing means operatively connected to said second decoder means for comparing the input connected to the input terminal selected by said second decoder means with the condition specified by said input instruction in said instruction register means; address modifying means operatively connected to said memory address register means for modifying said program address in said memory address register means; destination address reading means operatively connected to said main memory means for reading out the destination address in said main memory means addressed by said memory address register means; temporary register means operatively connected to said main memory means for storing said destination address read out by said destination address reading means; writing means operatively connected to said auxiliary memory means for writing said destination address in said temporary register means into the same location of said auxiliary memory means from which said program address was read out by said address reading Means; means operatively connected to said program select register means for causing said program select register means to select a different program address after said destination address is written into said auxiliary memory means by said writing means: and program control means coupled to said comparing means and responsive to the result of the comparison by said comparing means for modifying said program address in said memory address register means so as to skip to read out said destination address in said main memory means only when said result of said comparison is satisfactory.

Claim 7

A programmable logic controller for controlling a device having at least one input and at least one output comprising: main memory means for storing a plurality of programs, each of said plurality of programs consisting of a sequence of instructions including input and output instructions and destination addresses; auxiliary memory means for storing a plurality of program addresses corresponding to said plurality of programs; program select register means operatively connected to said auxiliary memory means for selecting one of said plurality of program addresses stored in said auxiliary memory means; address reading means operatively connected to said auxiliary memory means for reading out the program address in said auxiliary memory means selected by said program select register means; memory address register means operatively connected to said main memory means and to said auxiliary memory means for addressing said main memory means with said program address read out by said address reading means; instruction reading means operatively connected to said main memory means for reading out the input and output instruction in said main memory means addressed by said memory address register means; instruction register means operatively connected to said main memory means for storing said input and output instruction read out by said instruction reading means; input and output control circuit means operatively connected to said instruction register means and to said device and having a plurality of input terminals to which said at least one input of said device is connected and a plurality of output terminals to which said at least one output of said device is connected, said input and output control circuit means including a decoder means operatively connected to said instruction register means for selecting one of said plurality of output terminals specified by an output instruction in said instruction register means, means operatively connected to said decoder means for energizing and deenergizing output connected to the output terminal selected by said decoder means in accordance with said output instruction in said instruction register means, a second decoder means operatively connected to said instruction register means for selecting one of said plurality of input terminals specified by an input instruction in said instruction register means, comparing means operatively connected to said second decoder means for comparing the input connected to the input terminal selected by said second decoder means with the condition specified by said input instruction in said instruction register means; address modifying means operatively connected to said memory address register means for modifying said program address in said memory address register means; destination address reading means operatively connected to said main memory means for reading out the destination address in said main memory means addressed by said memory address register means; temporary register means operatively connected to said main memory means for storing said destination address read out by said destination address reading means; writing means operatively connected to said auxiliary memory means for writing said destination address in said temporary register means into the same location of said auxiliary memory means from which said program address wAs read out by said address reading means; means operatively connected to said program select register means for causing said program select register means to select a different program address after said destination address is written into said auxiliary memory means by said writing means: and program control means coupled to said comparing means and responsive to the result of the comparison by said comparing means for modifying said program address in said memory address register means so as to skip to read out said destination address in said main memory means only when said result of said comparison is unsatisfactory.

Claim 8

A programmable logic controller for controlling a device having at least one input and at least one output comprising: main memory means for storing a plurality of programs, each of said plurality of programs consisting of a sequence of instructions including input and output instructions and destination addresses; auxiliary memory means for storing a plurality of program addresses corresponding to said plurality of programs; program select register means operatively connected to said auxiliary memory means for selecting one of said plurality of program addresses stored in said auxiliary memory means; address reading means operatively connected to said auxiliary memory means for reading out the program address in said auxiliary memory means selected by said program select register means; memory address register means operatively connected to said main memory means and to said auxiliary memory means for addressing said main memory means with said program address read out by said address reading means; instruction reading means operatively connected to said main memory means for reading out the input and output instruction in said main memory means addressed by said memory address register means; instruction register means operatively connected to said main memory means for storing said input and output instruction read out by said instruction reading means; input and output control circuit means operatively connected to said instruction register means and to said device and having a plurality of input terminals to which said at least one input of said device is connected and a plurality of output terminals to which said at least one output of said device is connected, said input and output control circuit means including a decoder means operatively connected to said instruction register means for selecting one of said plurality of output terminals specified by an output instruction in said instruction register means, means operatively connected to said decoder means for energizing and deenergizing output connected to the output terminal selected by said decoder means in accordance with said output instruction in said instruction register means, a second decoder means operatively connected to said instruction register means for selecting one of said plurality of input terminals specified by an input instruction in said instruction register means, comparing means operatively connected to said second decoder means for comparing the input connected to the input terminal selected by said second decoder means with the condition specified by said input instruction in said instruction register means; address modifying means operatively connected to said memory address register means for modifying said program address in said memory address register means; destination address reading means operatively connected to said main memory means for reading out the destination address in said main memory means addressed by said memory address register means; temporary register means operatively connected to said main memory means for storing said destination address read out by said destination address reading means; writing means operatively connected to said auxiliary memory means for writing said destination address in said temporary register means into the same location of said auxiliary memory means from which said program address wAs read out by said address reading means; means operatively connected to said program select register means for causing said program select register means to select a different program address after said destination address is written into said auxiliary memory means by said writing means: and program control means coupled to said comparing means and responsive to the result of the comparison by said comparing means for modifying said program address in said memory address register means so as to skip to read out said destination address in said main memory means only when said result of said comparison is unsatisfactory.

Claim 9

A programmable logic controller for controlling a plurality of devices, each of said plurality of devices having at least one input and at least one output comprising: main memory means for storing a plurality of programs, each of said plurality of programs consisting of a sequence of instructions including input and output instructions and destination addresses; auxiliary memory means for storing a plurality of sets of program addresses corresponding to said plurality of devices, each of said sets of program addresses corresponding to said plurality of programs stored in said main memory means; program select register means operatively connected to said auxiliary memory means for selecting one program address of said plurality of sets of program addresses stored in said auxiliary memory means; address reading means operatively connected to said auxiliary memory means for reading out the program address in said auxiliary memory means selected by said program select register means; memory address register means operatively connected to said main memory means and to said auxiliary memory means for addressing said main memory means with said program address read out by said address reading means; instruction reading means operatively connected to said main memory means for reading out the input and output instruction in said main memory means addressed by said memory address register means; instruction register means operatively connected to said main memory means for storing said input and output instruction read out by said instruction reading means; a plurality of input and output control circuit means operatively connected to said instruction register means and to said plurality of devices, each of which has a plurality of input terminals to which said at least one input of each of said plurality of devices is connected and a plurality of output terminals to which said at least one output of each of said plurality of devices is connected, each of said plurality of input and output control circuit means including a decoder means operatively connected to said instruction register means and to said program select register means for selecting one of said plurality of output terminals of each in said plurality of devices specified by an output instruction in said instruction register means, said decoder means for each of said plurality of devices being selectively activated by said program selected register means, means operatively connected to said decoder means for energizing and deenergizing the output connected to the output terminal selected by said decoder means in accordance with said output instruction in said instruction register means, a second decoder means operatively connected to said instruction register means and to said program select register means for selecting one of said plurality of input terminals of each of said plurality of devices specified by an input instruction in said instruction register means, said second decoder means for each of said plurality of devices being selectively activated by said program select register means and comparing means operatively connected to said second decoder means for comparing the input connected to the input terminal selected by said another decoder means with the condition specified by said input instruction in said instruction means; addreSs modifying means operatively connected to said memory address register means for modifying said program address in said memory address register means; destination address reading means operatively connected to said main memory means for reading out the destination address in said main memory means addressed by said memory address register means; temporary register means operatively connected to said main memory means for storing said destination address read out by said destination address reading means; writing means operatively connected to said auxiliary memory means for writing said destination address in said temporary register means into the same location of said auxiliary memory means from which said program address was read out by said address reading means; means operatively connected to said program select register means for causing said program select register means to select a different program address after said destination address is written into said auxiliary memory means; and program control means responsive to the result of the comparison by said comparing means for modifying said program address in said memory address register means so as to skip to read out said destination address only when said result of said comparison is satisfactory.

Claim 10

A programmable logic controller for controlling a plurality of devices, each of said plurality of devices having at least one input and at least one output comprising: main memory means for storing a plurality of programs, each of said plurality of programs consisting of a sequence of instructions including input and output instructions and destination addresses; auxiliary memory means for storing a plurality of sets of program addresses corresponding to said plurality of devices, each of said sets of program addresses corresponding to said plurality of programs stored in said main memory means; program select register means operatively connected to said auxiliary memory means for selecting one program address of said plurality of sets of program addresses stored in said auxiliary memory means; address reading means operatively connected to said auxiliary memory means for reading out the program address in said auxiliary memory means selected by said program select register means; memory address register means operatively connected to said main memory means and to said auxiliary memory means for addressing said main memory means with said program address read out by said address reading means; instruction reading means operatively connected to said main memory means for reading out the input and output instruction in said main memory means addressed by said memory address register means; instruction register means operatively connected to said main memory means for storing said input and output instruction read out by said instruction reading means; a plurality of input and output control circuit means operatively connected to said instruction register means and to said plurality of devices, each of which has a plurality of input terminals to which said at least one input of each of said plurality of devices is connected and a plurality of output terminals to which said at least one output of each of said plurality of devices is connected, each of said plurality of input and output control circuit means including a decoder means operatively connected to said instruction register means and to said program select register means for selecting one of said plurality of output terminals of each in said plurality of devices specified by an output instruction in said instruction register means, said decoder means for each of said plurality of devices being selectively activated by said program selected register means, means operatively connected to said decoder means for energizing and deenergizing the output connected to the output terminal selected by said decoder means in accordance with said output instruction in said instruction register means, a second decoder means operatively connected to said instruction register means and to said program select register means for selecting one of said plurality of input terminals of each of said plurality of devices specified by an input instruction in said instruction register means, said second decoder means for each of said plurality of devices being selectively activated by said program select register means and comparing means operatively connected to said second decoder means for comparing the input connected to the input terminal selected by said another decoder means with the condition specified by said input instruction in said instruction means; addreSs modifying means operatively connected to said memory address register means for modifying said program address in said memory address register means; destination address reading means operatively connected to said main memory means for reading out the destination address in said main memory means addressed by said memory address register means; temporary register means operatively connected to said main memory means for storing said destination address read out by said destination address reading means; writing means operatively connected to said auxiliary memory means for writing said destination address in said temporary register means into the same location of said auxiliary memory means from which said program address was read out by said address reading means; means operatively connected to said program select register means for causing said program select register means to select a different program address after said destination address is written into said auxiliary memory means; and program control means responsive to the result of the comparison by said comparing means for modifying said program address in said memory address register means so as to skip to read out said destination address only when said result of said comparison is satisfactory.

Claim 11

A programmable logic controller for controlling a plurality of devices, each of said plurality of devices having at least one input and at least one output comprising: main memory means for storing a plurality of programs, each of said plurality of programs consisting of a sequence of instructions including input and output instructions and destination addresses; auxiliary memory means for storing a plurality of sets of program addresses corresponding to said plurality of devices, each of said sets of program addresses corresponding to said plurality of programs stored in said main memory means; program select register means operatively connected to said auxiliary memory means for selecting one program address of said plurality of sets of program addresses stored in said auxiliary memory means; address reading means operatively connected to said auxiliary memory means for reading out the program address in said auxiliary memory means selected by said program select register means; memory address register means operatively connected tO said main memory means and to said auxiliary memory means for addressing said main memory means with said program address read out by said address reading means; instruction reading means operatively connected tO said main memory means for reading out the input and output instruction in said main memory means addressed by said memory address register means; instruction register means operatively connected to said main memory means for storing said input and output instruction read out by said instruction reading means; a plurality of input and output control circuit means operatively connected to said instruction register means and to said plurality of devices, each of which has a plurality of input terminals to which said at least one input of each of said plurality of devices is connected and a plurality of output terminals to which said at least one output of each of said plurality of devices is connected, each of said plurality of input and output control circuit means including a decoder means operatively connected to said instruction register means and to said program select register means for selecting one of said plurality of output terminals of each of said plurality of devices specified by an output instruction in said instruction register means, said decoder means for each of said plurality of devices being selectively activated by said program selected register means, means operatively connected to said decoder means for energizing and deenergizing the output connected to the output terminal selected by said decoder means in accordance with said output instruction in said instruction register means, a second dEcoder means operatively connected to said instruction register means and to said program select register means for selecting one of said plurality of input terminals of each of said plurality of devices specified by an input instruction in said instruction register means, said second decoder means for each of said plurality of devices being selectively activated by said program select register means and comparing means operatively connected to said second decoder means for comparing the input connected to the input terminal selected by said another decoder means with the condition specified by said input instruction in said instruction means; address modifying means operatively connected to said memory address register means for modifying said program address in said memory address register means; destination address reading means operatively connected to said main memory means for reading out the destination address in said main memory means addressed by said memory address register means; temporary register means operatively connected to said main memory means for storing said destination address read out by said destination address reading means; writing means operatively connected to said auxiliary memory means for writing said destination address in said temporary register means into the same location of said auxiliary memory means from which said program address was read out by said address reading means; means operatively connected to said program select register means for causing said program select register means to select a different program address after said destination address is written into said auxiliary memory means; and program control means responsive to the result of the comparison by said comparing means for modifying said program address in said memory address register means so as to skip to read out said destination address only when said result of said comparison is unsatisfactory.

Claim 12

A programmable logic controller for controlling a plurality of devices, each of said plurality of devices having at least one input and at least one output comprising: main memory means for storing a plurality of programs, each of said plurality of programs consisting of a sequence of instructions including input and output instructions and destination addresses; auxiliary memory means for storing a plurality of sets of program addresses corresponding to said plurality of devices, each of said sets of program addresses corresponding to said plurality of programs stored in said main memory means; program select register means operatively connected to said auxiliary memory means for selecting one program address of said plurality of sets of program addresses stored in said auxiliary memory means; address reading means operatively connected to said auxiliary memory means for reading out the program address in said auxiliary memory means selected by said program select register means; memory address register means operatively connected tO said main memory means and to said auxiliary memory means for addressing said main memory means with said program address read out by said address reading means; instruction reading means operatively connected tO said main memory means for reading out the input and output instruction in said main memory means addressed by said memory address register means; instruction register means operatively connected to said main memory means for storing said input and output instruction read out by said instruction reading means; a plurality of input and output control circuit means operatively connected to said instruction register means and to said plurality of devices, each of which has a plurality of input terminals to which said at least one input of each of said plurality of devices is connected and a plurality of output terminals to which said at least one output of each of said plurality of devices is connected, each of said plurality of input and output control circuit means including a decoder means operatively connected to said instruction register means and to said program select register means for selecting one of said plurality of output terminals of each of said plurality of devices specified by an output instruction in said instruction register means, said decoder means for each of said plurality of devices being selectively activated by said program selected register means, means operatively connected to said decoder means for energizing and deenergizing the output connected to the output terminal selected by said decoder means in accordance with said output instruction in said instruction register means, a second dEcoder means operatively connected to said instruction register means and to said program select register means for selecting one of said plurality of input terminals of each of said plurality of devices specified by an input instruction in said instruction register means, said second decoder means for each of said plurality of devices being selectively activated by said program select register means and comparing means operatively connected to said second decoder means for comparing the input connected to the input terminal selected by said another decoder means with the condition specified by said input instruction in said instruction means; address modifying means operatively connected to said memory address register means for modifying said program address in said memory address register means; destination address reading means operatively connected to said main memory means for reading out the destination address in said main memory means addressed by said memory address register means; temporary register means operatively connected to said main memory means for storing said destination address read out by said destination address reading means; writing means operatively connected to said auxiliary memory means for writing said destination address in said temporary register means into the same location of said auxiliary memory means from which said program address was read out by said address reading means; means operatively connected to said program select register means for causing said program select register means to select a different program address after said destination address is written into said auxiliary memory means; and program control means responsive to the result of the comparison by said comparing means for modifying said program address in said memory address register means so as to skip to read out said destination address only when said result of said comparison is unsatisfactory.

Claim 13

A programmable logic controller for controlling a plurality of devices, each of said plurality of devices having at least one input and at least one output comprising: main memory means for storing a plurality of programs, each of said plurality of programs consisting of a sequence of instructions including input and output instructions and destination addresses; auxiliary memory means for storing a plurality of sets of program addresses corresponding to said plurality of devices, each of said sets of program addresses corresponding to said plurality of programs stored in said main memory means; program select register means operatively connected to said auxiliary memory means for selecting one program address of said plurality of sets of program addresses stored in said auxiliary memory means; address reading means operatively connected to said auxiliary memory means for reading out the program address in said auxiliary memory means selected by said program select register means; memory address register means operatively connected to said main memory means and to said auxiliary memory means for addressing said main memory means with said program address read out by said address reading means; instruction reading means operatively connected to said main memory means for reading out the input and output instruction in said main memory means addressed by said memory address register means; instruction register means operatively connected to said main memory means for storing said input and output instruction read out by said instruction reading means; input and output control circuit means operatively connected to said instruction register means and to said plurality of devices, which has a plurality of sets of input terminals and a plurality of sets of output terminals, said at least one input of each of said plurality of devices being connected to each of said sets of input terminals and said at least one output of each of said plurality of devices being connected to each of said sets of output teRminals, said input and output control circuit means including a plurality of decoder means operatively connected to said instruction register means and to said program select register means, each of said plurality of decoder means provided for selecting one of said sets of input terminals and one of said sets of output terminals specified by an input and output instruction in said instruction register means, said plurality of decoder means corresponding to said plurality of devices and one of said plurality of decoder means being selectively activated by said program select register means, means operatively connected to said plurality of decoder means for energizing and deenergizing the output connected to the output terminal selected by said plurality of decoder means in accordance with an output instruction in said instruction register means and comparing means operatively connected to said plurality of decoder means for comparing the input connected to the input terminal selected by said plurality of decoder means with the condition specified by an input instruction in said instruction means; address modifying means operatively connected to said memory address register means for modifying said program address in said memory address register means; destination address reading means operatively connected to said main memory means for reading out the destination address in said main memory means addressed by said memorY address register means; temporary register means operatively connected to said main memory means for storing said destination address read out by said destination address reading means; writing means operatively connected to said auxiliary memory means for writing said destination address in said temporary register means into the same location of said auxiliary memory means from which said program address was read out by said address reading means; means operatively connected to said program select register means for causing said program select register means to select a different program address after said destination address is written into said auxiliary memory means; and program control means responsive to the result of the comparison by said comparing means for modifying said program address in said memory address register means so as to skip to read out said destination address only when said result of said comparison is satisfactory.

Claim 14

A programmable logic controller for controlling a plurality of devices, each of said plurality of devices having at least one input and at least one output comprising: main memory means for storing a plurality of programs, each of said plurality of programs consisting of a sequence of instructions including input and output instructions and destination addresses; auxiliary memory means for storing a plurality of sets of program addresses corresponding to said plurality of devices, each of said sets of program addresses corresponding to said plurality of programs stored in said main memory means; program select register means operatively connected to said auxiliary memory means for selecting one program address of said plurality of sets of program addresses stored in said auxiliary memory means; address reading means operatively connected to said auxiliary memory means for reading out the program address in said auxiliary memory means selected by said program select register means; memory address register means operatively connected to said main memory means and to said auxiliary memory means for addressing said main memory means with said program address read out by said address reading means; instruction reading means operatively connected to said main memory means for reading out the input and output instruction in said main memory means addressed by said memory address register means; instruction register means operatively connected to said main memory means for storing said input and output instruction read out by said instruction reading means; input and output control circuit means operatively connected to said instruction register means and to said plurality of devices, which has a plurality of sets of input terminals and a plurality of sets of output terminals, said at least one input of each of said plurality of devices being connected to each of said sets of input terminals and said at least one output of each of said plurality of devices being connected to each of said sets of output teRminals, said input and output control circuit means including a plurality of decoder means operatively connected to said instruction register means and to said program select register means, each of said plurality of decoder means provided for selecting one of said sets of input terminals and one of said sets of output terminals specified by an input and output instruction in said instruction register means, said plurality of decoder means corresponding to said plurality of devices and one of said plurality of decoder means being selectively activated by said program select register means, means operatively connected to said plurality of decoder means for energizing and deenergizing the output connected to the output terminal selected by said plurality of decoder means in accordance with an output instruction in said instruction register means and comparing means operatively connected to said plurality of decoder means for comparing the input connected to the input terminal selected by said plurality of decoder means with the condition specified by an input instruction in said instruction means; address modifying means operatively connected to said memory address register means for modifying said program address in said memory address register means; destination address reading means operatively connected to said main memory means for reading out the destination address in said main memory means addressed by said memorY address register means; temporary register means operatively connected to said main memory means for storing said destination address read out by said destination address reading means; writing means operatively connected to said auxiliary memory means for writing said destination address in said temporary register means into the same location of said auxiliary memory means from which said program address was read out by said address reading means; means operatively connected to said program select register means for causing said program select register means to select a different program address after said destination address is written into said auxiliary memory means; and program control means responsive to the result of the comparison by said comparing means for modifying said program address in said memory address register means so as to skip to read out said destination address only when said result of said comparison is satisfactory.

Claim 15

A programmable logic controller for controlling a plurality of devices, each of said plurality of devices having at least one input and at least one output comprising: main memory means for storing a plurality of programs, each of said plurality of programs consisting of a sequence of instructions including input and output instructions and destination addresses; auxiliary memory means for storing a plurality of sets of program addresses corresponding to said plurality of devices, each of said sets of program addresses corresponding to said plurality of programs stored in said main memory means; program select register means operatively connected to said auxiliary memory means for selecting one program address of said plurality of sets of program addresses stored in said auxiliary memory means; address reading means operatively connected to said auxiliary memory means for reading out the program address in said auxiliary memory means selected by said program select register means; memory address register means operatively connected to said main memory means and to said auxiliary memory means for addressing said main memory means with said program address read out by said address reading means; instruction reading means operatively connected to said main memory means for reading out the input and output instruction in said main memory means addressed by said memory address register means; instruction register means operatively connected to said main memory means for storing said input and output instruction read out by said instruction reading means; input and output control circuit means operatively connected to said instruction register means and to said plurality of devices, which has a plurality of sets of input terminals and a plurality of sets of output terminals, said at least one input of each of said plurality of devices being connected to each of said sets of input terminals and said at least one output of each of said plurality of devices being connected to each of said sets of output terminals, said input and output control circuit means including a plurality of decoder means operatively connected to said instruction register means and to said program select register means, each of said plurality of decoder means provided for selecting one of said sets of input terminals and one of said sets of output terminals specified by an input and output instruction in said instruction register means, said plurality of decoder means corresponding to said plurality of devices and one of said plurality of decoder means being selectively activated by said program select register means, means operatively connected to said plurality of decoder means for energizing and deenergizing the output connected to the output terminal selected by said plurality of decoder means in accordance with an output instruction in said instruction register means and comparing means operatively connected to said plurality of decoder means for comparing the input connected to the input terminal selected by said plurality of decoder means with the condition specified by an input instruction in said instruction means; address modifying means operatively connected to said memory address register means for modifying said program address in said memory address register means; destination address reading means operatively connected to said main memory means for reading out the destination address in said main memory means addressed by said memory address register means; temporary register means operatively connected to said main memory means for storing said destination address read out by said destination address reading means; writing means operatively connected to said auxiliary memory means for writing said destination address in said temporary register means into the same location of said auxiliary memory means from which said program address was read out by said address reading means; means operatively connected to said program select register means for causing said program select register means to select a different program address after said destination address is written into said auxiliary memory means; and program control means responsive to the result of the comparison by said comparing means for modifying said program address in said memory address register means so as to skip to read out said destination address only when said result of said comparison is unsatisfactory.

Claim 16

A programmable logic controller for controlling a plurality of devices, each of said plurality of devices having at least one input and at least one output comprising: main memory means for storing a plurality of programs, each of said plurality of programs consisting of a sequence of instructions including input and output instructions and destination addresses; auxiliary memory means for storing a plurality of sets of program addresses corresponding to said plurality of devices, each of said sets of program addresses corresponding to said plurality of programs stored in said main memory means; program select register means operatively connected to said auxiliary memory means for selecting one program address of said plurality of sets of program addresses stored in said auxiliary memory means; address reading means operatively connected to said auxiliary memory means for reading out the program address in said auxiliary memory means selected by said program select register means; memory address register means operatively connected to said main memory means and to said auxiliary memory means for addressing said main memory means with said program address read out by said address reading means; instruction reading means operatively connected to said main memory means for reading out the input and output instruction in said main memory means addressed by said memory address register means; instruction register means operatively connected to said main memory means for storing said input and output instruction read out by said instruction reading means; input and output control circuit means operatively connected to said instruction register means and to said plurality of devices, which has a plurality of sets of input terminals and a plurality of sets of output terminals, said at least one input of each of said plurality of devices being connected to each of said sets of input terminals and said at least one output of each of said plurality of devices being connected to each of said sets of output terminals, said input and output control circuit means including a plurality of decoder means operatively connected to said instruction register means and to said program select register means, each of said plurality of decoder means provided for selecting one of said sets of input terminals and one of said sets of output terminals specified by an input and output instruction in said instruction register means, said plurality of decoder means corresponding to said plurality of devices and one of said plurality of decoder means being selectively activated by said program select register means, means operatively connected to said plurality of decoder means for energizing and deenergizing the output connected to the output terminal selected by said plurality of decoder means in accordance with an output instruction in said instruction register means and comparing means operatively connected to said plurality of decoder means for comparing the input connected to the input terminal selected by said plurality of decoder means with the condition specified by an input instruction in said instruction means; address modifying means operatively connected to said memory address register means for modifying said program address in said memory address register means; destination address reading means operatively connected to said main memory means for reading out the destination address in said main memory means addressed by said memory address register means; temporary register means operatively connected to said main memory means for storing said destination address read out by said destination address reading means; writing means operatively connected to said auxiliary memory means for writing said destination address in said temporary register means into the same location of said auxiliary memory means from which said program address was read out by said address reading means; means operatively connected to said program select register means for causing said program select register means to select a different program address after said destination address is written into said auxiliary memory means; and program control means responsive to the result of the comparison by said comparing means for modifying said program address in said memory address register means so as to skip to read out said destination address only when said result of said comparison is unsatisfactory.