Data processing system having an instruction pipeline for concurrently processing a plurality of instructions

Claim 2

A data processing system having storage apparatus, instruction handling apparatus and instruction execution apparatus wherein the system performs data manipulations under the control of instructions where each instruction is processed in segments where each segment has a duration equal to a number of clock cycles, the improvement comprising, clock means providing clock signals which define clock cycles for controlling the data processing system, instruction sequence processing means including at least three stages where said stages include at least three register means for storing instructions and where said stages include control means responsive to information in said register means for controlling said storage apparatus and said instruction execution apparatus, means for sequentially stepping a plurality of segmented instructions through said stages with a time-offset between instructions equal to an integral number, greater than unity and less than five, of clock cycles.

Claim 3

The data processing system of claim 1 wherein said time-offset is two clock cycles.

Claim 4

The data processing system of claim 1 wherein each instruction is processed in thirteen segments and where said segments are processed in one or more clock cycles.

Claim 5

The data processing system of claim 3 wherein said instruction segments are PFO, IA, IB1, IB2, D, R, OA, OB1, OB2, E1, E2, CK, and W and wherein said system includes means for prefetch offset formation operative during said PFO segment, means for instruction address formation operative during said IA segment, means for instruction buffer access initiation operative during said IB1 segment, means for instruction buffer access completion operative during said IB2 segment, means for instruction decoding operative during said D segment, means for reading address data operative during said R segment, means for operand address formation operative during said OA segment, means for operand buffer access initiation operative during said OB1 segment, means for operand buffer access completion operative during said OB2 segment, means for execution initiation operative during said E1 segment, means for execution completion operative during said E2 segment, means for checking operative during said CK segment, and means for writing operative during said W segment.

Claim 6

The data processing system of claim 2 wherein the execution apparatus includes a plurality of functional Units for executing instructions, where said functional units are each operative to perform a data manipulation once per cycle and where at least two functional units are connected in series to operate over two cycles of said data processing system.

Claim 7

The data processing system of claim 2 wherein said instruction execution apparatus includes, a first functional unit responsive to said instruction sequence processing means for executing logical, comparison and checking functions over a first cycle of the data processing system, a second functional unit connected to receive the output from said first functional unit and responsive to said instruction sequence processing means for executing additions over a second cycle of the data processing system whereby the execution time for data manipulations in said first and second functional units equals two cycles and also equals the timeoffset of instructions in said instruction sequence processing means.

Claim 8

The data processing system of claim 6 wherein said execution apparatus further includes a multiplier functional unit, a shifter functional unit, and a byte adder functional unit each connected in parallel with said second functional unit and each operable over said second cycle and each connected in series to receive an output from said first functional unit whereby the execution time for data manipulations in said execution apparatus equals at least two cycles and equals the time-offset of instructions in said instruction processing means.

Claim 9

The data processing system of claim 1 wherein said instruction sequence processing means includes a plurality of address registers for storing address values to be added in forming effective addresses, an effective address adder connected to receive the information stored in said address registers, an effective address register for storing the output from said effective address adder, an instruction pipeline including a plurality of shift register stages for storing said instructions during sequential segments of the instruction sequence processing, sequential control means for causing the effective address in the effective address register to access instructions from said storage apparatus and transfer said instructions into said instruction pipeline.

Claim 10

The data processing system of claim 8 wherein the segments for each instruction include PFO for prefetch offset formation, IA for instruction address formation, IB1 for instruction buffer access initiation, IB2 for instruction buffer access completion, D for instruction decoding, R for reading address data, OA for operand address formation, OB1 for operand buffer access initiation, OB2 for operand buffer access completion, E1 for execution initiation, E2 for execution completion, CK for checking, W for writing and wherein said instruction sequence processing means includes, a first stage operative over said D and R segments of each instruction and having a first register for storing said instruction at the end of said R segment; a second stage responsive to said first register and operative over said OA and OB1 segments of each instruction and having a second register for storing said instruction at the end of said OB1 segment; a third stage responsive to said second register and operative over said OB2 and E1 segments of each instruction and having a third register for storing said instruction at the end of said E1 segment; a fourth stage responsive to said third register and operative over said E2 segment of each instruction and having a fourth register for storing said instruction at the end of said E2 segment; a fifth stage responsive to said fourth register and operative over said CK segment of each instruction and having a fifth register for storing said instruction at the end of said CK segment; and includes a sixth stage responsive to said fifth register and operative over said W segment of each instruction, control means for sequentIally stepping said instructions through said instruction sequence processing means.

Claim 11

The data processing system of claim 9 wherein said instruction sequence processing means includes, means operative over said PFO segment of each instruction to store address information in said address registers, means operative over said IA segment of each instruction to gate effective address information to said adder from said addressing registers whereby said adder forms an effective address in said effective address register, means operative over said IB1 segment of each instruction to transfer the effective address from said effective address register to said storage apparatus to initiate accessing of an instruction, means operative over said IB2 segment of each instruction to complete accessing of the addressed instruction in said storage apparatus.

Claim 12

The data processing system of claim 10 wherein said storage apparatus is addressable and accessable within two cycles of said data processing system and includes a storage unit, a buffer address register for addressing said storage unit over said IB1 and said OB1 segments of each instruction, and a plurality of registers for fetching and storing data in data locations addressed by said buffer address register over said IB2 and said OB2 segments of each instruction.

Claim 13

The data processing system of claim 1 wherein said execution apparatus requires at least two clock cycles to perform data manipulations, wherein said storage apparatus accesses storage locations therein for fetching or storing data in at least two clock cycles of said data processing system, and wherein said means for sequentially stepping includes means for stepping said instructions with a time-offset equal to two clock cycles of said data processing system.

Claim 14

The data processing system of claim 12 wherein said system is operative, in response to said instruction sequence processing means, to process instructions requiring two accesses to said storage apparatus, one access for instruction fetching and one access for operand fetching, said accesses to said storage apparatus being carried out in response to said instruction sequence processing means by common accessing circuitry in said instruction handling apparatus and said storage apparatus whereby the accessing for instruction fetching in a first instruction and the accessing for operand fetching in a second instruction occur at different times because the time-offset of instructions within the instruction sequence processing means equals two clock cycles.

Claim 15

The data processing system of claim 8 wherein said instruction sequence processing means includes, an instruction word register for receiving instructions, an instruction buffer register for latching instructions received from said instruction word register, selection means responsive to said sequential control means for selecting the instruction next to be introduced into said instruction pipeline from said instruction buffer register or from said instruction word register.

Claim 16

The data processing system of claim 8 wherein said instruction sequence processing means includes a plurality of general purpose registers, input registers for storing information to be stored in said general purpose registers, and output registers for storing information readout from said general purpose registers, wherein said general purpose registers are connected to be accessed under control of a first one of said stages for latching address information in one of said plurality of address registers.

Claim 17

In a data processing system having storage apparatus, instruction handling apparatus and instruction execution apparatus wherein said instruction handling apparatus includes instruction sequence processing means having at least three serial stages each for controlling different parts of said system and wherein said apparatus is operative under control of clock cycles and operative to execute instrucTions where each instruction is executed in segments where each segment has a duration equal to a number of clock cycles and where predetermined stages are active for predetermined segments of each instruction, the improved method comprising, introducing at least three of said instructions serially into said stages with a time-offset between instructions equal to an integral number, greater than unity, of clock cycles, stepping said segmented instructions through said processing means with said time-offset equal to said number of clock cycles.

Claim 18

In a data processing system having storage apparatus, instruction handling apparatus and instruction execution apparatus wherein said instruction handling apparatus includes instruction sequence processing means having at least three serial stages each for controlling different parts of said system and wherein said apparatus is operative under control of clock cycles and operative to execute instrucTions where each instruction is executed in segments where each segment has a duration equal to a number of clock cycles and where predetermined stages are active for predetermined segments of each instruction, the improved method comprising, introducing at least three of said instructions serially into said stages with a time-offset between instructions equal to an integral number, greater than unity, of clock cycles, stepping said segmented instructions through said processing means with said time-offset equal to said number of clock cycles.

Claim 19

A data processing system having storage apparatus, instruction handling apparatus, and instruction execution apparatus for performing data manipulations under the timing control of clock cycles and operative to execute instructions where each instruction is executed in segments where each segment has a duration equal to at least one clock cycle, the improvement comprising, high-speed buffer means within said storage apparatus operative to be accessed for storing and fetching data within two clock cycles, a plurality of functional units within said execution apparatus wherein at least two of said functional units are serially connected whereby said execution apparatus carries out data manipulations within two clock cycles, instruction sequence processing means within said instruction handling apparatus including a plurality of serial stages, said stages including one stage operative over two consecutive segments of each instruction to control said buffer means and said stages including another stage operative over two different consecutive segments of each instruction to control said two of said functional units, including means for introducing a plurality of segmented instructions into said stages with a time-offset between instructions at least equal to two clock cycles.

Claim 20

A data processing system having storage apparatus, instruction handling apparatus, and instruction execution apparatus for performing data manipulations under the timing control of clock cycles and operative to execute instructions where each instruction is executed in segments where each segment has a duration equal to at least one clock cycle, the improvement comprising, high-speed buffer means within said storage apparatus operative to be accessed for storing and fetching data within two clock cycles, a plurality of functional units within said execution apparatus wherein at least two of said functional units are serially connected whereby said execution apparatus carries out data manipulations within two clock cycles, instruction sequence processing means within said instruction handling apparatus including a plurality of serial stages, said stages including one stage operative over two consecutive segments of each instruction to control said buffer means and said stages including another stage operative over two different consecutive segments of each instruction to control said two of said functional units, including means for introducing a plurality of segmented instructions into said stages with a time-offset between instructions at least equal to two clock cycles.

Claim 21

A data processing system having clock apparatus for producing clock signals having clock cycles, a main store, a storage control unit operative to address and access data in two clock cycles, a channel unit, an instruction unit, an execution unit operative to perform arithmetic and logical functions in two clock cycles, and a console wherein the system performs data manipulations specified by a stored program comprised of a sequence of instructions, wherein each instruction is executed in segments where each segment has a duration equal to one clock cycle, the improvement comprising, instruction sequence processing means including a plurality of address registers for storing address values to be added in forming effective addresses, an effective address adder connected to receive the information stored in said address registers, an effective address register for storing the output from said effective address adder, an instruction pipeline including a plurality of shift-register stages for storing instructions fetched from said storage control unit and including control means each for controlling different parts of said system during different segments of each instruction, sequential control means for causing the effective address in the effective address register to access instructions from said storage apparatus for transfer into said instruction pipeline with a time-offset between consecutive instructions equal to two clock cycles.

Claim 22

A data processing system having clock apparatus for producing clock signals having clock cycles, a main store, a storage control unit operative to address and access data in two clock cycles, a channel unit, an instruction unit, an execution unit operative to perform arithmetic and logical functions in two clock cycles, and a console wherein the system performs data manipulations specified by a stored program comprised of a sequence of instructions, wherein each instruction is executed in segments where each segment has a duration equal to one clock cycle, the improvement comprising, instruction sequence processing means including a plurality of address registers for storing address values to be added in forming effective addresses, an effective address adder connected to receive the information stored in said address registers, an effective address register for storing the output from said effective address adder, an instruction pipeline including a plurality of shift-register stages for storing instructions fetched from said storage control unit and including control means each for controlling different parts of said system during different segments of each instruction, sequential control means for causing the effective address in the effective address register to access instructions from said storage apparatus for transfer into said instruction pipeline with a time-offset between consecutive instructions equal to two clock cycles.

Claim 23

A data processing system having storage apparatus, instruction handling apparatus and instruction execution apparatus wherein the system performs data manipulations under the control of instructions where instructions are processed at a maximum rate in segments where each segment has a duration equal to one clock cycle, the improvement comprising, clock means providing clock signals which define clock cycles for controlling the data processing system, instruction sequence processing means including a plurality of stages where said plurality of stages include at least five registers for storing instructions and where said stages include control means responsive to information in Said registers for controlling said storage apparatus and said instruction execution apparatus, means for sequentially stepping a plurality of said instructions through said stages with a time-offset between consecutive instructions in said registers equal to two clock cycles.

Claim 24

A data processing system having storage apparatus, instruction handling apparatus and instruction execution apparatus wherein the system performs data manipulations under the control of instructions where instructions are processed at a maximum rate in segments where each segment has a duration equal to one clock cycle, the improvement comprising, clock means providing clock signals which define clock cycles for controlling the data processing system, instruction sequence processing means including a plurality of stages where said plurality of stages include at least five registers for storing instructions and where said stages include control means responsive to information in Said registers for controlling said storage apparatus and said instruction execution apparatus, means for sequentially stepping a plurality of said instructions through said stages with a time-offset between consecutive instructions in said registers equal to two clock cycles.