US3838397A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Fuel injection pulse width computer
Assignee: Boeing North American Inc
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Filing: 1973-04-25
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Granted: 1974-09-24
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Expires: 1993-04-25
Abstract
Abstract A real time, digital computer is used to calculate a pulse width, for example, for fuel injection systems. The computer uses data from environmental sensors, data stored internally in fixed memories and an instruction program stored internally in a further fixed memory to calculate the pulse width. In fuel injection systems, the pulse width determines the length of time a fuel injector is operative during each engine cycle.
Inventors
- 👤 G Watson
- 👤 G Griffith
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 16:39
CPC Classifications
F; F02; F02D; F02D41/00; F02D41/009; F02D41/24; F02D41/2403; F02D41/26; F02D41/30; F02D41/32; F02D41/34; F02M; F02M51/00; G; G06; G06F; G06F1/00; G06F1/02; G06F1/03; Y; Y02; Y02T; Y02T10/00; Y02T10/10; Y02T10/40
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
149 words
In combination, a plurality of source means, control means, logic means connected to receive signals from said source means and said control means, data memory means connected to receive signals from said logic means and to supply information from memory locations addressed by said signals from said logic means, accumulator means connected to receive the information from said memory locations and to operate thereon to produce sum signals, output memory means connected to said accumulator means to receive and operate upon only a first portion of said sum signals and to supply an output memory signal as a function of the portion of said sum signals supplied to said output memory means, and output register means connected to receive said output memory signal and a second portion of said sum signals from said accumulator means to selectively alter the output memory signal previously stored in said output register means.
Claim 2
Dependent Claim
149 words
In combination, a plurality of source means, control means, logic means connected to receive signals from said source means and said control means, data memory means connected to receive signals from said logic means and to supply information from memory locations addressed by said signals from said logic means, accumulator means connected to receive the information from said memory locations and to operate thereon to produce sum signals, output memory means connected to said accumulator means to receive and operate upon only a first portion of said sum signals and to supply an output memory signal as a function of the portion of said sum signals supplied to said output memory means, and output register means connected to receive said output memory signal and a second portion of said sum signals from said accumulator means to selectively alter the output memory signal previously stored in said output register means.
Claim 3
Dependent Claim
49 words
The combination recited in claim 1 including storage means connected to said accumulator means for storing current information from said accumulator means during the insertion of new information therein and for subsequently retiring of said current information to said accumulator means for combination with the new information stored therein.
Claim 4
Dependent Claim
57 words
The combination recited in claim 1 including function memory means connected to said accumulator means and said control means whereby the information in said accumulator means operates as an address signal for said function memory means, said function memory means connected to supply information at the memory location addressed by said address signal to said accumulator means.
Claim 5
Dependent Claim
62 words
The combination recited in claim 1 wherein said control means includes program memory means, and program address counter means, said program address counter means comprises a free running counter which is connected to supply signals to said program memory means in order to step said program memory means through the instruction program stored therein to control the functions of the entire combination.
Claim 6
Dependent Claim
37 words
The combination recited in claim 1 wherein each of said memory means includes a plurality of memory locations, each of said memory means is a read only memory which has specific information stored at each memory location.
Claim 7
Dependent Claim
75 words
The combination recited in claim 1 including scaler means connected between said data memory means and said accumulator means to operate upon and modify the information from said memory locations before transfer to said accumulator means, and address means connected between said logic means and said accumulator means to operate upon the signals from said logic means to change the memory location in said data memory means addressed by the signals from said address means.
Claim 8
Dependent Claim
17 words
The combination recited in claim 1 wherein said signals and said information are arranged in digital form.
Claim 9
Dependent Claim
21 words
The combination recited in claim 1 wherein said accumulator means is connected to supply address signals to said data memory means.
Claim 10
Dependent Claim
21 words
The combination recited in claim 1 wherein said output memory means is connected to supply information signals to said accumulator means.
Claim 11
Dependent Claim
35 words
The combination recited in claim 6 wherein said address means includes means for operating upon the signals from said logic means by incrementing a portion thereof and providing a one''s complement of another portion thereof.
Claim 12
Dependent Claim
15 words
The combination recited in claim 1 wherein output memory means stores information in logarithmic form.
Claim 13
Dependent Claim
17 words
The combination recited in claim 11 wherein said output memory means stores information in an antilog form.
Claim 14
Dependent Claim
56 words
The combination recited in claim 3 wherein said output register means is connected to receive signals from said output memory means and store the signals so received, said output register means further connected to said accumulator means to receive signals from said function memory means which alter the signals previously stored in said output register means.
Claim 15
Dependent Claim
47 words
The combination recited in claim 1 wherein said logic means includes means for combining the signals received from said source means and the signals received from said control means to produce address signals for selecting the memory locations in said data memory means which will supply information.
Claim 16
Dependent Claim
66 words
The combination recited in claim 1 which produces output signals from said output register means in accordance with the algorithm PW PWSB (1 + ESiKSij) where PW is the final pulse width of the output signal, PWSB is a base pulse width determined by first source SB, ESi is the enrichment factor determined by the respective source Si, and KSij are constants related to source Si.
Claim 17
Dependent Claim
18 words
The combination recited in claim 1 wherein said sources include transducers for producing signals representative of environmental conditions.
Claim 18
Dependent Claim
15 words
The combination recited in claim 1 including utilization means connected to said output register means.
Claim 19
Dependent Claim
93 words
The combination recited in claim 4 wherein said program memory means includes a plurality of memory locations, each of said memory locations has an instruction of said instruction program stored therein, each instruction is in the form of a multibit digital signal, said program memory means connected to supply each instruction to said logic means in accordance with the operation of said program address counter means, each instruction enables a selected portion of said logic means whereby selected signals from said source means are transferred to said data memory means as address signals.
Claim 20
Dependent Claim
35 words
The combination recited in claim 1 wherein said accumulator means includes means for cumulatively storing information supplied thereto whereby the information stored in said accumulator means represents the instantaneous total of all information supplied thereto.
Claim 21
Dependent Claim
62 words
The combination recited in claim 19 wherein the information stored in said accumulator means represents an address in a portion of said data memory means, said accumulator means and said portion of said data memory means interconnected so that the information stored at the appropriate address in said portion of said data memory means is transferred to said accumulator means when addressed.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-09-23 | 1978-03-25 | 1978-09-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-09-23 | 1982-03-25 | 1982-09-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-09-23 | 1986-03-25 | 1986-09-24 | $7700.00 | Window Closed / Lapsed |