US3838339A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Logic test probe and indicator circuit
Assignee: AG Communication Systems Corp
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Filing: 1973-08-17
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Granted: 1974-09-24
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Expires: 1993-08-17
Abstract
Abstract A test circuit for detecting low, high and open voltage levels, and dynamically changing voltage levels in a digital circuit includes a display panel and a probe provided with a plurality of indicators for signalling each of the possible level conditions sensed by the probe. The circuit also includes a current detecting circuit for providing an unambiguous indication when an open level is present. A pair of indicators provide information of the presence of dynamically changing levels while low and high level indicators provide information by way of duty cycles of the shape of the dynamic wave-form. An indicator is also provided for giving a sustained indication when an unexpected level change takes place and includes means for automatically resetting itself.
Inventors
- 👤 W Brandt
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 15:09
CPC Classifications
G; G01; G01R; G01R19/00; G01R19/165; G01R19/16533; G01R19/16557
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
288 words
A test circuit for detecting low, high and open static voltage levels or dynamically changing voltage levels at any given point of a digital circuit comprising: an Electrically conductive probe; a display panel including a. a low level voltage indicator b. a high level voltage indicator c. an open voltage indicator d. a pair of dynamic voltage indicators and e. a change-of-voltage indicator; a low level voltage detector coupled between said probe and said low level indicator for activating said low level indicator when said probe detects a low level voltage; a high level voltage detector coupled between said probe and said high level indicator and including means responsive to current flow in said probe for activating said high level indicator when said probe detects a current flow and a high level voltage; open level control means having a first input coupled to said low level detector and a second input coupled to said high level detector and an output coupled to said open voltage indicator for activating said open voltage indicator when there is an absence of a low and a high level indication at the outputs of said low level detector and said high level detector; a dynamic voltage detector between said probe and said dynamic voltage indicators for activating said dynamic voltage indicators when the levels at said probe are dynamically changing; and a change-of-voltage detector coupled between said probe and said change-of-voltage indicator for activating and causing it to provide a sustained indication when a voltage change occurs at said probe; whereby, said open voltage indicator provides a separate positive indication of an open voltage, and said change-of-voltage indicator provides a sustained indication of a voltage change to allow it to be readily observed.
Claim 2
Dependent Claim
288 words
A test circuit for detecting low, high and open static voltage levels or dynamically changing voltage levels at any given point of a digital circuit comprising: an Electrically conductive probe; a display panel including a. a low level voltage indicator b. a high level voltage indicator c. an open voltage indicator d. a pair of dynamic voltage indicators and e. a change-of-voltage indicator; a low level voltage detector coupled between said probe and said low level indicator for activating said low level indicator when said probe detects a low level voltage; a high level voltage detector coupled between said probe and said high level indicator and including means responsive to current flow in said probe for activating said high level indicator when said probe detects a current flow and a high level voltage; open level control means having a first input coupled to said low level detector and a second input coupled to said high level detector and an output coupled to said open voltage indicator for activating said open voltage indicator when there is an absence of a low and a high level indication at the outputs of said low level detector and said high level detector; a dynamic voltage detector between said probe and said dynamic voltage indicators for activating said dynamic voltage indicators when the levels at said probe are dynamically changing; and a change-of-voltage detector coupled between said probe and said change-of-voltage indicator for activating and causing it to provide a sustained indication when a voltage change occurs at said probe; whereby, said open voltage indicator provides a separate positive indication of an open voltage, and said change-of-voltage indicator provides a sustained indication of a voltage change to allow it to be readily observed.
Claim 3
Dependent Claim
17 words
A test circuit in accordance with claim 1 wherein said display panel indicators are light emitting diodes.
Claim 4
Dependent Claim
45 words
A test circuit in accordance with claim 1 wherein said low level voltage detector comprises a serially coupled inverter and NAND gate, the input of said inverter coupled to said probe and the output of said NAND gate coupled to said low level voltage indicator.
Claim 5
Dependent Claim
28 words
A test circuit in accordance with claim 1 wherein said means responsive to current flow comprises a pulse shaper conditioned to respond to current flow in said probe.
Claim 6
Dependent Claim
100 words
A test circuit in accordance with claim 1 wherein said high level voltage detector comprises a serially coupled inverter and first NAND gate, a second NAND gate and a pulse shaper responsive to current flow in said probe, the input of said inverter and an input of said pulse shaper coupled to said probe, the output of said first NAND gate coupled to an input of said second NAND gate, the output of said pulse shaper coupled to another input of said second NAND gate, and the output of said second NAND gate coupled to said high level voltage indicator.
Claim 7
Dependent Claim
18 words
A test circuit in accordance with claim 1 wherein said open level control means comprises a NAND gate.
Claim 8
Dependent Claim
97 words
A test circuit in accordance with claim 1 wherein said dynamic voltage detector comprises a first and second NAND gate and a flip-flop having a pair of outputs and a clock input coupled to said probe, said flip-flop being conditioned to provide at said outputs reciprocally changing high and low voltage levels in response to the level changes at said probe, each said flip-flop outputs coupled to the input of an assigned one of said NAND gates, and the output of each said NAND gate coupled to an assigned one of said pair of dynamic voltage indicators.
Claim 9
Dependent Claim
28 words
A test circuit in accordance with claim 1 wherein said change-of-voltage detector includes means for resetting itself after said indication has been sustained for a predetermined time period.
Claim 10
Dependent Claim
80 words
A test circuit in accordance with claim 1 wherein said change-of-voltage detector comprises a flip-flop having a clock input coupled to said probe and an output, and a NAND gate having an input and an output, said flip-flop output coupled to said NAND gate input, said NAND gate output coupled to said change-of-voltage indicator, and Said flip-flop being conditioned to provide a sustained predetermined voltage level at said flip-flop output in response to the voltage level changes at said probe.
Claim 11
Dependent Claim
74 words
A test circuit in accordance with claim 9 wherein said change-of-voltage detector additionally includes a means for resetting itself comprising a pulse shaper having a first input coupled to said flip-flop output, a second input coupled to a source of electrical energy, and an output coupled to said flip-flop, said pulse shaper including means for providing at said output a resetting signal after said flip-flop output is sustained for a predetermined period of time.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-09-23 | 1978-03-25 | 1978-09-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-09-23 | 1982-03-25 | 1982-09-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-09-23 | 1986-03-25 | 1986-09-24 | $7700.00 | Window Closed / Lapsed |