Microprogrammable control memory diagnostic system

Claim 2

In a data processing system incorporating a central processing unit (CPU), main memory, and an input-output processor capable of loading a diagnostic program from a peripheral device into main memory, wherein said CPU comprises a control memory for storing and executing microprograms contained within said control memory to order said CPU through the steps required to perform said CPU''s arithmetic and logic functions, and data registers for storage of data being operated on by said CPU, the combination comprising: a test microprogram contained within said control memory of exercising circuits within said CPU and generating fault information therefrom, circuit means contained within said control memory for periodically executing said test microprogram, fault register means coupled to said circuit means for recording fault information generated by said test microprogram, and wherein said CPU further comprises transfer means for transferring said fault information and the contents of said data registers into said main memory for storage therein.

Claim 3

The combination of claim 1, wherein said fault register means further includes interrupt means responsive to the detection of a fault for generating a system interrupt, a set of instructions in main memory for ordering said transfer of said fault information, and further CPU circuit means responsive to said system interrupt for initiating execution of said set of instructions.

Claim 4

The combination in claim 2 including: software check-sum routines contained in main memory for testing transmission of data between peripheral devices and main memory, parity fault detection circuits responsive to the number of bits in words being processed by said CPU and contained within said CPU for testing parity of words being operated on by the data processing system, and means responsive to the detection of a fault by said software check-sum routines and said parity fault detection circuits for reporting said fault to said register means.

Claim 5

The combination in claim 3 including: terminal means remote from said data processing system site and coupled through telephone lines and through said input-output processor to said main memory for reading out said fault information and the contents of said data registers.

Claim 6

In a data processing system incorporating a central processing unit (CPU), main memory, an input-output processor capable of loading a diagnostic program from a peripheral device into main memory, a remote terminal coupled to said CPU through telephone lines and said input-output processor, wherein said CPU comprises a control memory within said CPU for storing and executing microprograms contained within said control memory to order said CPU through thE steps required to perform said CPU''s arithmetic and logic functions, and data registers for storage of data being operated on by said CPU, the method comprising: testing of circuits within said CPU by means of a test microprogram located in said control memory and executed periodically, transferring to main memory for storage therein fault information generated by the execution of said test microprogram defining the fault detected, and transferring to main memory for storage therein the contents of said data registers at the time of said fault detection.

Claim 7

In a data processing system incorporating a central processing unit (CPU), main memory, an input-output processor capable of loading a diagnostic program from a peripheral device into main memory, a remote terminal coupled to said CPU through telephone lines and said input-output processor, wherein said CPU comprises a control memory within said CPU for storing and executing microprograms contained within said control memory to order said CPU through thE steps required to perform said CPU''s arithmetic and logic functions, and data registers for storage of data being operated on by said CPU, the method comprising: testing of circuits within said CPU by means of a test microprogram located in said control memory and executed periodically, transferring to main memory for storage therein fault information generated by the execution of said test microprogram defining the fault detected, and transferring to main memory for storage therein the contents of said data registers at the time of said fault detection.

Claim 8

The method as set forth in claim 5 including the step of reading out said fault information and information contained in said data registers at said remote terminal.

Claim 9

The method as set forth in claim 6 wherein the step of testing comprises the steps of: measuring the time since the test microprogram was last executed, generating a request to initiate execution of said test microprogram upon the expiration of a pre-determined amount of time, comparing the test microprogram request priority against other concurrent program priorities, and initiating the execution of said test microprogram when it has the highest priority.

Claim 10

In a data processing system incorporating a central processing unit CPU, main memory, an input-out processor for transferring information between a peripheral device and said main memory, and a remote terminal coupled through telephone lines and said input-out processor to said CPU, wherein said CPU contains at least one microprogrammable control memory and data registers for storage of data being operated on by said CPU, the method comprising: testing of said control memory and the circuits within said central processing unit by means of a test microprogram located in said control memory, transferring to main memory for storage therein information defining the fault detected by said testing and the contents of said data registers at the time of said fault detection, and reading out of said fault information and said contents of said data registers at said remote terminal.

Claim 11

In a data processing system incorporating a central processing unit CPU, main memory, an input-out processor for transferring information between a peripheral device and said main memory, and a remote terminal coupled through telephone lines and said input-out processor to said CPU, wherein said CPU contains at least one microprogrammable control memory and data registers for storage of data being operated on by said CPU, the method comprising: testing of said control memory and the circuits within said central processing unit by means of a test microprogram located in said control memory, transferring to main memory for storage therein information defining the fault detected by said testing and the contents of said data registers at the time of said fault detection, and reading out of said fault information and said contents of said data registers at said remote terminal.

Claim 12

The method in claim 8 wherein said step of testing comprises the step of: identifying the specific fault detected, and wherein said transferring step comprises the steps of: forcing the data processing system into a wait state to preserve the status of all circuits, generating an interrupt which initiates a software error-logging routine, logging fault and system information in main memory by means of said software error-logging routine, and returning the data processing system to its normal function.

Claim 13

In a data processing system of the type having a main memory for storing data and program words, a central processing unit (CPU) for reading said data and program words from said main memory, for performing arithmetic and logic operations upon said words and for storing said words into said main memory, and a control memory within said CPU for storing and executing microprograms contained within said control memory to order said CPU through the steps required to perform said CPU functions, an improved diagnostic method comprising the steps of: measuring the time since a diagnostic microprogram was last executed, generating a request to initiate execution of said diagnostic microprogram upon the expiration of a pre-determined amount of time, comparing the diagnostic microprogram request priority against other concurrent program priorities, initiating the execution of said diagnostic microprogram when it has the highest priority, identifying a specific fault, forcing the CPU into a wait state to preserve the current contents of all CPU registers, generating an interrupt to initiate a software error-logging program, logging fault information and CPU register contents in main memory by means of said error-logging programs, and returning the data procEssing system to its original functions.

Claim 14

In a data processing system of the type having a main memory for storing data and program words, a central processing unit (CPU) for reading said data and program words from said main memory, for performing arithmetic and logic operations upon said words and for storing said words into said main memory, and a control memory within said CPU for storing and executing microprograms contained within said control memory to order said CPU through the steps required to perform said CPU functions, an improved diagnostic method comprising the steps of: measuring the time since a diagnostic microprogram was last executed, generating a request to initiate execution of said diagnostic microprogram upon the expiration of a pre-determined amount of time, comparing the diagnostic microprogram request priority against other concurrent program priorities, initiating the execution of said diagnostic microprogram when it has the highest priority, identifying a specific fault, forcing the CPU into a wait state to preserve the current contents of all CPU registers, generating an interrupt to initiate a software error-logging program, logging fault information and CPU register contents in main memory by means of said error-logging programs, and returning the data procEssing system to its original functions.