Statistical noise processor

Claim 2

Statistical signal processing apparatus for enhancing the readability of repetitive spectrum analysis samples of a noise signal comprising in combination: timing means having an input for receiving a signal at the beginning of each sample and for providing at least four sequentially timed pulses; first calculating means for receiving each sample and connected to receive the ultimate and penultimate of said pulses, respectively, and for calculating the mean, the variance and the third moment of each sample in response to said ultimate and penultimate pulses and for producing signals representative thereof; delay means connected to receive said first calculating means signals and the remaining of said pulses for providing first, second and third delayed signals indicative of the difference between the means, the variances and third moments, respectively, of sequential ones of the samples; second calculating means connected to receive said delay means signals for calculating the square root of the difference between a first higher order moment and the square of a second higher order moment of the sample and for producing a signal having an amplitude representative of the enhanced spectrum analysis samples.

Claim 3

Signal processing apparatus according to claim 1 wherein said first calculating means further comprises: first processing means connected to receive each sample and the ultimate and penultimate pulses for integrating and storing said sample in response to said ultimate and penultimate pulses to produce an output signal indicative of the mean thereof; second processing means having an input connected to receive each sample and the ultimate and penultimate pulses for integrating and storing said sample in response to said ultimate and penultimate pulses to produce an output signal indicative of the variance thereof; and third processing means having an input connected to receive said second processing means output signal and the ultimate and penultimate pulses for integrating and storing said second processing means output signal in response to said ultimate and penultimate pulses to produce an output signal indicative of the third moment thereof.

Claim 4

Signal processing apparatus according to claim 2 wherein said first processing means further comprises; a first integrator connected to receive each sample and the ultimate pulse for integrating the sample in response to said ultimate pulse and to produce a signal representative thereof; and first storage means connected to receive said first integrator signal and the penultimate pulse for storing the value of said integrator signal at the end of each sample in response to said penultimate pulse and to produce said first processing means output signal.

Claim 5

Signal processing apparatus according to claim 3 wherein said second processing means further comprises: a first multiplier connected to receive each sample for producing a signal representative of the squared value of each sample; a second integrator connected to receive said first multiplier signal and the ultimate pulse for integrating said multiplier signal in response to said ultimate pulse and to produce a signal representative thereof; and second storage means connected to receive said second integrator signal and the penultimate pulse for storing the value of said second integrator signal at the end of each sample in response to said penultimate pulse and to produce said second processing means output signal.

Claim 6

Signal processing apparatus according to claim 4 wherein said third processing means further comprises: a third integrator operatively connected to receive said second processing means output signal and connected to receive the ultimate pulse for integrating said second processing means output signal in response to said ultimate pulse and to produce a signal representative thereof; and third storage means connected to receive said third integrator signal and the penultimate pulse for storing the value of said third integrator signal at the end of each sample in response to said penultimate pulse and to produce said third processing means output signal.

Claim 7

Signal processing apparatus according to claim 5 wherein said delay means further comprises: first difference means connected to receive said first processing means output signal for producing the mean difference between said sequential ones of the samples and providing a first output signal representative thereof; second difference means connected to receive said second processing means output signal for producing the variance difference between said sequential ones of the samples and providing a second output signal representative thereof; and third difference means having an input connected to receive said third processing means output signal for producing the third moment difference between said sequential ones of the samples and providing a third output signal representative thereof.

Claim 8

Signal processing apparatus according to claim 6 wherein said first, second and third difference means each further comprises: holding means connected to receive individual ones of said first calculating means signals and the remainder of said timing means pulses for sequentially storing a plurality of said ones of said first calculating means signals in response to said remaining pulses and for providing a first signal representative of a first stored signal and a second signal representative of a later stored signal; inverting means connected to receive said holding means second signal for inverting the polarity of said second signal and producing a signal representative thereof; and adding means connected to receive said holding means first signal and said inverting means signal for producing the delayed differential signals of said delay means.

Claim 9

Signal processing means according to claim 7 wherein said holding means includes a plurality of serially connected sample and hold circuits.

Claim 10

Signal processing means according to claim 8 wherein said second calculating means further comprises: a first divider having a first input connected to receive said delay means first signal and a second input connected to receive said delay means second signal for dividing said second input by said first input and producing a quotient thereof; a first inverter connected to receive said delay means first signal for inverting the polarity of said delay means first signal and for producing a signal representative thereof; a first summer having a first input connected to receive said quotient and a second input connected to receive said first inverter signal for producing a signal representative of the sum thereof; a second multiplier connected to receive said first summer signal for producing a signal representative of the squared value thereof; a second inverter connected to receive said second multiplier signal for inverting the polarity of said second multiplier signal and for producing a signal representative thereof; a third multiplier connected to receive said delay means first signal for producing a signal representative of the squared value thereof; a second divider having a first input connected to receive said delay means first signal and a second input connected to receive said delay means third signal for dividing said second input by said first input and producing a quotient thereof; a second summer having a first input connected to receive said delay means second signal, a second input connected to receive said second inverter signal, a third input connected to receive said third multiplier signal and a fourth input connected to receive said second divider quotient for producing a signal representative of the sum thereof; and root means connected to receive said second summer signal for producing a signal representative of the square root thereof.

Claim 11

Signal processing apparatus according to claim 1 further comprising in combination: recording means for receiving said second calculating means signal for producing a lofargram replica thereof.