US3832640A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Time division interpolator
Assignee: Ford Motor Co
•
Filing: 1972-12-11
•
Granted: 1974-08-27
•
Expires: 1992-12-11
Abstract
Abstract An electronic circuit is disclosed for generating an output signal having a frequency which is a selected multiple of a variable input signal frequency. To obtain the desired multiplication, a relatively high clock signal frequency is divided by a number which corresponds to the selected multiple to produce a second signal having a lower frequency than the clock signal frequency. The individual pulses of the lower frequency signal are counted during the time interval between two consecutive input signal pulses to generate a second, variable, number which is then used to divide the clock signal frequency in the time period immediately following the occurrence of the second of the two consecutive input signal pulses. The resulting output signal therefore occurs at a frequency which is equal to the frequency of the input signal multiplied by the desired multiplicative factor.
Inventors
- 👤 A Cederquist
- 👤 S Devlin
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-22 18:56
CPC Classifications
G; G01; G01P; G01P3/00; G01P3/42; G01P3/44; G01P3/48; G01P3/481; G01P3/489; G06; G06F; G06F7/00; G06F7/60; G06F7/68
Claims Analysis
Total Claims: 24
Claim 1
Independent Claim
143 words
A circuit for generating a selected number of output pulses in response to a received input signal pulse, wherein the frequency of the input signal may vary, comprising in combination: means for receiving the input signal pulses; clock means for generating a clock signal having a frequency greatly in excess of the input signal; first divider means for generating a first signal having a pulse frequency equal to the clock signal frequency divided by a first integer; first counter means responsive to the received input signal operative to receive and count the number of first signal pulses occurring between two input signal pulses to generate a second integer signal; second divider means responsive to said first counter means and to said clock means for generating an output signal having a pulse frequency equal to the clock signal frequency divided by the second integer.
Claim 2
Dependent Claim
143 words
A circuit for generating a selected number of output pulses in response to a received input signal pulse, wherein the frequency of the input signal may vary, comprising in combination: means for receiving the input signal pulses; clock means for generating a clock signal having a frequency greatly in excess of the input signal; first divider means for generating a first signal having a pulse frequency equal to the clock signal frequency divided by a first integer; first counter means responsive to the received input signal operative to receive and count the number of first signal pulses occurring between two input signal pulses to generate a second integer signal; second divider means responsive to said first counter means and to said clock means for generating an output signal having a pulse frequency equal to the clock signal frequency divided by the second integer.
Claim 3
Dependent Claim
21 words
The circuit of claim 1 wherein the value of the first integer is equal to the value of the selected number.
Claim 4
Dependent Claim
58 words
The circuit of claim 1 wherein said first divider means comprise: second counter means receiving the clock signal and operative to repeatably count the number of clock signal pulses received up to the value of the first integer and further operative to generate an output signal pulse every time the count reaches the value of the first integar.
Claim 5
Dependent Claim
83 words
The circuit of claim 1 wherein said secoNd divider means comprise: means responsive to the first counter means for receiving and storing a signal representative of the second integer; and third counter means responsive to the receiving and storing means and receiving the clock signal operative to repeatably count the number of clock signal pulses received to the value of the second integer and further operative to generate an output signal pulse every time the count reaches the value of the second integer.
Claim 6
Dependent Claim
47 words
The circuit of claim 1 including further control means responsive to each input signal pulse to terminate the count of said first counter means to thereby determine the value of the second integer; and storage means responsive to the control means for storing the second integer value.
Claim 7
Dependent Claim
58 words
The circuit of claim 5 wherein said first divider means comprise: second counter means receiving the clock signal and operative to repeatably count the number of clock signal pulses received up to the value of the first integer and further operative to generate an output signal pulse every time the count reaches the value of the first integer.
Claim 8
Dependent Claim
83 words
The circuit of claim 6 wherein said second divider means comprise: means responsive to the first counter means for receiving and storing a signal representative of the second integer; and third counter means responsive to the receiving and storing means and receiving the clock signal operative to repeatably count the number of clock signal pulses received to the value of the second integer and further operative to generate an output signal pulse every time the count reaches the value of the second integer.
Claim 9
Independent Claim
128 words
A method for converting a variable frequency input signal at a relatively low frequency to an output signal at a relatively high frequency which is a selected multiple of the input signal frequency comprising: receiving the input signal; generating a clock signal having a frequency which is high compared to the maximum desired output signal frequency; dividing the clock signal by a value which corresponds to the selected multiple to produce a signal having a frequency which corresponds to the clock signal frequency divided by the selected multiple; counting the number of pulses in the divided clock signal which occur between two input signal pulses to generate a number signal; and dividing the clock signal by the number represented by the number signal to produce the output signal.
Claim 10
Independent Claim
128 words
A method for converting a variable frequency input signal at a relatively low frequency to an output signal at a relatively high frequency which is a selected multiple of the input signal frequency comprising: receiving the input signal; generating a clock signal having a frequency which is high compared to the maximum desired output signal frequency; dividing the clock signal by a value which corresponds to the selected multiple to produce a signal having a frequency which corresponds to the clock signal frequency divided by the selected multiple; counting the number of pulses in the divided clock signal which occur between two input signal pulses to generate a number signal; and dividing the clock signal by the number represented by the number signal to produce the output signal.
Claim 11
Dependent Claim
47 words
The method of claim 8 wherein the step of dividing the clock signal by a value which corresponds to the selected multiple comprises: counting each clock signal pulse; and generating an output signal pulse each time the count reaches the value which corresponds to the selected multiple.
Claim 12
Dependent Claim
86 words
The method of claim 8 wherein the step of dividing the clock signal by the number represented by the number signal comprises the steps of: storing the number represented by the number signal; and dividing the clock signal by the generated number for a period of time following the second of the two input signal pulses until a third input signal occurs, the third input signal having the same relationship to the second input signal as the second input signal has to the first input signal.
Claim 13
Dependent Claim
75 words
The method of claim 8 wherein the step of dividing the clock signal by the number represented by the number signal comprises the steps of: storing the number represented by the number signal; nondestructively reading the stored number to establish a count value; counting clock signal pulses until the count equals the count value; generating an output signal when the count equals the count value; and repeating the last named reading count and generating steps.
Claim 14
Dependent Claim
23 words
The method of claim 11 wherein the step of storing the number include the step of storing the binary complement of the number.
Claim 15
Dependent Claim
64 words
The method of claim 12 wherein the steps of reading the stored number and counting the clock signal pulses comprise the steps of: nondestructively reading the binary complement of the stored number to set an initial count value; adding the pulses of the clock signal to the initial value to increase the initial value; and detecting the attainment of a predetermined maximum count value.
Claim 16
Dependent Claim
111 words
In a circuit for receiving a variable frequency input signal and generating an output signal having a frequency which is a fixed high multiple of the input signal frequency, the improvement comprising: variable-modulo counter means operative to receive a high frequency clock signal and a number signal and responsive thereto to generate an output signal at a frequency equal to the clock signal frequency divided by the received number; counter means for counting the number of pulses of a predetermined frequency pulse signal which occur between two input signal pulses; and storage means for storing a number representative of the count and for communicating this number to the variable-modulo counter means.
Claim 17
Dependent Claim
111 words
In a circuit for receiving a variable frequency input signal and generating an output signal having a frequency which is a fixed high multiple of the input signal frequency, the improvement comprising: variable-modulo counter means operative to receive a high frequency clock signal and a number signal and responsive thereto to generate an output signal at a frequency equal to the clock signal frequency divided by the received number; counter means for counting the number of pulses of a predetermined frequency pulse signal which occur between two input signal pulses; and storage means for storing a number representative of the count and for communicating this number to the variable-modulo counter means.
Claim 18
Dependent Claim
38 words
The circuit of claim 14 wherein the counter means comprise a binary counter and the storage means comprise means for storing the binary representation of the number counted and for storing the binary complement of the number counted.
Claim 19
Dependent Claim
44 words
The circuit of claim 15 wherein the variable modulo counter means comprise a binary up-counter and the number generator means are operative to establish an initial count value, said initial count value being the binary complement of the number counted by the counter means.
Claim 20
Dependent Claim
49 words
The circuit of claim 16 including further signal generator means responsive to the binary upcounter operative to generate the output signal; said signal generator means including a binary 1''s detector means responsive to the variable-modulo counter means operative to detect a maximum count condition of said variable-modulo counter means.
Claim 21
Dependent Claim
50 words
The circuit as claimed in claim 14 wherein said signal generator means further include means responsive to the binary 1''s detector to generate an output signal on the occurrence of a signal indicative of a maximum count and thereafter operative to generate a signal for reestablishing the initial count value.
Claim 22
Dependent Claim
85 words
The circuit as claimed in claim 17 wherein said signal generator means comprise bistable gating means responsive to the clock signal and to the binary 1''s detector operative to generate a high going output signal in response to the binary 1''s detector detecting a condition of a maximum number count by the binary up-counter and also operative to generate a signal for reducing the count value to equal the initial count value whereby the output signal will be terminated to produce an output signal pulse.
Claim 23
Independent Claim
138 words
A method for generating a selected number of pulse signals in response to a pulse of an input signal having a variable pulse frequency, the output signal frequency being variable in response to variations in the input signal frequency, comprising the steps of: generating a clock signal having a frequency which is high with respect to the maximum desired output signal frequency; dividing the clock signal by a fixed divisor number to produce a lower frequency signal; counting the number of pulses of said lower frequency signal occurring between two input signal pulses; storing the count number; and, subsequent to the occurrence of the second of the two input signal pulses, dividing the clock signal by a variable number which is a function of the stored number and of the fixed divisor number to generate the output signal.
Claim 24
Independent Claim
138 words
A method for generating a selected number of pulse signals in response to a pulse of an input signal having a variable pulse frequency, the output signal frequency being variable in response to variations in the input signal frequency, comprising the steps of: generating a clock signal having a frequency which is high with respect to the maximum desired output signal frequency; dividing the clock signal by a fixed divisor number to produce a lower frequency signal; counting the number of pulses of said lower frequency signal occurring between two input signal pulses; storing the count number; and, subsequent to the occurrence of the second of the two input signal pulses, dividing the clock signal by a variable number which is a function of the stored number and of the fixed divisor number to generate the output signal.
References Cited (Backward Citations)
US3375448A
Cited
US3375449A
Cited
US3484699A
Cited
US3581116A
Cited
US3657658A
Cited
US3673391A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-08-26 | 1978-02-25 | 1978-08-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-08-26 | 1982-02-25 | 1982-08-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-08-26 | 1986-02-25 | 1986-08-27 | $7700.00 | Window Closed / Lapsed |