High-speed analog-to-digital converter

Claim 1

In an analog-to-digital converter having first and second comparator means, each having first and second input terminals and an output terminal, each comparator means providing a binary output signal of a first value when a signal at said first input terminal is greater than a signal at said second input terminal and a binary output signal of the other value when a signal at said first input terminal is less than a signal at said second input terminal; means for coupling said input terminals of said comparator means to a source of reference potential and to an analog signal input means so that the output signals of said comparator means exhibit like binary values only when the amplitude of said analog signal is between the respective reference potentials applied to said comparator means; and flip-flop means having input means, complementary output means and a clock input means for receiving a clock signal, for providing a binary output signal value complementary to the binary input value at said complementary output means in response to a clock signal being applied to said clock input means; the improvement comprising: means for coupling the output signals of said first and second comparator means to said input means of said flip-flop means to provide a phantom logic gate, whereby the logical sum of the output signals of said first and second comparator means provides a binary input signal at said input means of said flip-flop, said binary input signal being a signal of one binary value when the amplitude of said analog signal is between the reference potentials applied to said first and second comparator means, and a signal of the opposite binary value when the amplitude of said analog signal is not between the reference potentials applied to said first and second comparator means, and the complement of said binary input signal is provided at said complementary output means of said flip-flop means in response to said clock signal without adding a gate delay.