US3828321A — System for reconfiguring central processor and in…

Claim 1

Independent Claim 399 words

A programmable data processing system having first and second central data processors each including processing circuits and maintenance circuits, and first and second storage means, one of said storage means being adapted respectively to be connected in signal communication with one of said central processors and the other storage means being adapted to be connected in signal communication with the other central data processor under normal operating conditions, said maintenance circuits sensing conditions within said system to generate error signals upon detection of faults, said system further including a system recovery program, wherein the improvement comprises: subsystem circuit means in each data processor for connecting said first and second central processors with said first and second storage means to form predetermined configurations thereof, one of said central processors being active and the other being passive at any one time, said subsystem comprising recovery control circuit means including state control circuit means for generating state signals representative of a plurality of predetermined states, and control logic circuit means responsive to said error signals to actuate said state control circuit to generate said state signals in predetermined order as defined by the circuitry of said state control circuit means, sAid state signals including a central processor switch signal for determining one central processor as being active and corresponding to at least one state change, and further including a storage means switch signal in one of said states for determining one storage means as being primary and being associated with said active central processor corresponding to a desired storage means being coupled with the active central processor, said recovery control circuit means further including means for generating a system recovery signal to initiate said system recovery program when either of said central processor switch signal or said storage means switch signal is generated; maintenance access circuit means responsive to program controlled signals for generating configuration signals representative of a desired configuration of said central processors and storage means; and configuration control circuit means responsive to said central processor switch signal and said storage means switch signal of said recovery control circuit means and responsive to said configuration signals of said maintenance access circuit means, and including a first switching circuit means for controlling the switching of said central processors and second switching circuit means for controlling the coupling of said first and second storage means with said first and second central processors.

Claim 2

Dependent Claim 399 words

A programmable data processing system having first and second central data processors each including processing circuits and maintenance circuits, and first and second storage means, one of said storage means being adapted respectively to be connected in signal communication with one of said central processors and the other storage means being adapted to be connected in signal communication with the other central data processor under normal operating conditions, said maintenance circuits sensing conditions within said system to generate error signals upon detection of faults, said system further including a system recovery program, wherein the improvement comprises: subsystem circuit means in each data processor for connecting said first and second central processors with said first and second storage means to form predetermined configurations thereof, one of said central processors being active and the other being passive at any one time, said subsystem comprising recovery control circuit means including state control circuit means for generating state signals representative of a plurality of predetermined states, and control logic circuit means responsive to said error signals to actuate said state control circuit to generate said state signals in predetermined order as defined by the circuitry of said state control circuit means, sAid state signals including a central processor switch signal for determining one central processor as being active and corresponding to at least one state change, and further including a storage means switch signal in one of said states for determining one storage means as being primary and being associated with said active central processor corresponding to a desired storage means being coupled with the active central processor, said recovery control circuit means further including means for generating a system recovery signal to initiate said system recovery program when either of said central processor switch signal or said storage means switch signal is generated; maintenance access circuit means responsive to program controlled signals for generating configuration signals representative of a desired configuration of said central processors and storage means; and configuration control circuit means responsive to said central processor switch signal and said storage means switch signal of said recovery control circuit means and responsive to said configuration signals of said maintenance access circuit means, and including a first switching circuit means for controlling the switching of said central processors and second switching circuit means for controlling the coupling of said first and second storage means with said first and second central processors.

Claim 3

Dependent Claim 186 words

The system of claim 1 wherein said state control circuit means of said recovery control circuit means comprises bistable circuit means for defining said states, said states including S0, S1, S2 and S3, and wired logic circuit means for controlling the state of said bistable circuit means wherein said bistable circuit means can switch in response to said error signals from state S0 only to state S1 and from state S1 only to state S2 and from state S2 only to state S3 and from state S3 only to state S2, said bistable circuit means being capable of being reset to state S0 from either of states S1, S2 or S3, said recovery control circuit means generating said central processor switch signal only if the standby central processor is capable of becoming active and whenever said bistable circuit means switches from said state S1 to state S2 or from state S3 to state S2, said recovery control circuit means further generating signals calling for said first storage means becoming primary in said state S2 and for said second storage means becoming primary in said state S3.

Claim 4

Dependent Claim 45 words

The system of claim 2 wherein said recovery control circuit means further comprises circuit means responsive to instruction signals from said system recovery program for switching from state S1 to state S2, from state S2 to state S3, and from state S3 to state S2.

Claim 5

Dependent Claim 38 words

The system of claim 1 further comprising input/output circuit means responsive to said second switching circuit means of said configuration control circuit means for selectively communicating a designated storage means as the primary storage means in a configuration.

Claim 6

Dependent Claim 52 words

The system of claim 4 wherein each of said storage means includes an address bus, a data bus and a return bus, and wherein said input/output circuit means include gating means for selectively communicating each of said buses of said storage means for communication with a selected one of said central processors.

Claim 7

Dependent Claim 73 words

The system of claim 5 wherein said second switching circuit means of said configuration control circuit means comprises a plurality of bistable circuits responsive to instruction signals received from said maintenance access circuit means for selecting predetermined ones of each of said buses of each of said storage means for selective communication with said central processors in accordance with a desired configuration, whereby independent program control over the resulting configuration may be achieved.

Claim 8

Dependent Claim 319 words

A programmable data processing system having first and second central data processors each including processing circuits and maintenance cIrcuits, and first and second storage means provided respectively with first and second bus means for coupling to said data processors, said maintenance circuits sensing conditions within said system to generate error signals upon detection of faults, said system further generating recovery reconfiguration instruction signals under program control, wherein the improvement comprises: sybsystem means in each data processor responsive to said error signals only when its associated data processor is active, for reconfiguring said first and second data processors and said first and second storage means to form new configurations thereof thereby to provide an active data processor and a standby data processor, said subsystem means including recovery control circuit means responsive to said error signals, and including state control circuit means for generating state signals representative of predetermined configuration states defined as S0, S1, S2 and S3, and control circuit means responsive to said error signals, and said state signals to further change the state of said state control circuit and to generate a set storage copy bus signal when said state control circuit is in said S2 state, and a switch processor signal both when said state control circuit is changing from said S1 state to said S2 state or from said S3 state to said S2 state; configuration control circuit means responsive to said recovery reconfiguration instruction signals, the configuration control circuit means in the active central processor being responsive to said switch processor signal only when the standby data processor is capable of becoming active and including a first circuit for controlling the switching of said data processors; and second bus control circuits for generating bus control signals; and input/output circuit means responsive to said bus control signals for connecting the designated storage means bus as the primary store bus coupled to the active central data processor.

Claim 9

Dependent Claim 319 words

A programmable data processing system having first and second central data processors each including processing circuits and maintenance cIrcuits, and first and second storage means provided respectively with first and second bus means for coupling to said data processors, said maintenance circuits sensing conditions within said system to generate error signals upon detection of faults, said system further generating recovery reconfiguration instruction signals under program control, wherein the improvement comprises: sybsystem means in each data processor responsive to said error signals only when its associated data processor is active, for reconfiguring said first and second data processors and said first and second storage means to form new configurations thereof thereby to provide an active data processor and a standby data processor, said subsystem means including recovery control circuit means responsive to said error signals, and including state control circuit means for generating state signals representative of predetermined configuration states defined as S0, S1, S2 and S3, and control circuit means responsive to said error signals, and said state signals to further change the state of said state control circuit and to generate a set storage copy bus signal when said state control circuit is in said S2 state, and a switch processor signal both when said state control circuit is changing from said S1 state to said S2 state or from said S3 state to said S2 state; configuration control circuit means responsive to said recovery reconfiguration instruction signals, the configuration control circuit means in the active central processor being responsive to said switch processor signal only when the standby data processor is capable of becoming active and including a first circuit for controlling the switching of said data processors; and second bus control circuits for generating bus control signals; and input/output circuit means responsive to said bus control signals for connecting the designated storage means bus as the primary store bus coupled to the active central data processor.

Claim 10

Dependent Claim 134 words

The system of claim 7 wherein said configuration control circuit means includes a processor active unit bistable circuit having a first section including first and second input leads and one output lead associated with one of said central processors and a second section having third and fourth input leads and a second output lead associated with the other of said central processors, said first and third input leads being cross-coupled with the other central processor whereby each of said sections may be made active only when the other section is inactive and said second and fourth input leads are responsive to the switch level signals of its associated recovery control circuit means, and wherein said first and second output leads generate signals representative respectively of an active level in one of said central processors.

Claim 11

Dependent Claim 57 words

The apparatus of claim 7 wherein said recovery control circuit means further includes a self-contained timing generator responsive to one of said error signals for generating timing signals to advance the state of said state control circuit means and to control the timing of the generation of said switch processor signal and said switch instruction store signal.

Claim 12

Dependent Claim 75 words

The system of claim 7 wherein said first and second bus means of said first and second storage means each includes an address bus, a data bus and a return bus, and wherein said input/output circuit means includes first gating circuitry for controlling the switching of said address bus, second gating circuitry for independently controlling the switching of said data bus, and third switching circuit means for independently controlling the switching of said return bus.

Claim 13

Dependent Claim 57 words

The system of claim 7 wherein said bus control circuits of said configuration control circuit means further includes a plurality of bistable circuits responsive to said copy bus signal of said recovery control circuit means and to programmed instruction signals for generating signals representative of a desired configuratioN of said storage means communicating with said central processors.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1977-08-05	1978-02-04	1978-08-06	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	1981-08-05	1982-02-04	1982-08-06	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	1985-08-05	1986-02-04	1986-08-06	$7700.00	Window Closed / Lapsed

System for reconfiguring central processor and instruction storage combinations

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