US3825926A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Interfacing circuitry for connecting a remote keyboard with a data receiving buffer
Assignee: International Business Machines Corp
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Filing: 1973-02-05
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Granted: 1974-07-23
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Expires: 1993-02-05
Abstract
Abstract Interfacing circuitry connected with a multiplexer activated by keyboard switches and providing an output on the application of a code thereto corresponding with a particular keyboard switch when actuated, the interfacing circuitry including a keyboard counter inhibited in its counting action by an output signal from the multiplexer on depression of one of the keyboard keys and supplying a code to the multiplexer, gating means for gating the content of the counter to a buffer, and delay means for delaying the gating action to the buffer until the expiration of a predetermined time after the raising of an output of the multiplexer. The delay means includes an oscillator driving a decode or counter providing timed successive output signals, and a plurality of flipflops under the control of these timing signals.
Inventors
- 👤 D Brownback
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 10:31
CPC Classifications
H; H03; H03M; H03M11/00; H03M11/20; G; G06; G06F; G06F3/00; G06F3/01; G06F3/02; G06F3/0227
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
306 words
Data transferring circuitry including a keyboard with a plurality of keys and key actuated switches, buffing means for holding data corresponding to one of said keys and its associated switch, a multiplexer having an input connected to each of said switches and having a control set of inputs to which encoded data is supplied so as to provide an outpu when data supplied to the latter inputs correspond to one of said keys and key actuated switches, a counter providing a coded output on a plurality of output lines and connected to said control set of inputs, an oscillator for driving said counter, means connecting said multiplexer and said counter for stopping said counter when said multiplexer has an output, gating means for gating said counter to said buffering means so that, when said gating means is open, the contents of said counter is supplied to said buffering means, and delay means having a first input connected with the output of said multiplexer and having an output connected to said gating means to control the gating means and rendered operative when said multiplexer has an output applied to said first input to be effective after a predetermined delay time after thus being rendered operative for causing said gating means to open to gate the contents of said counter to said buffering means with said counter being stopped, said delay means including a second input connected to the output of said multiplexer and including means under control of a signal on said second input for thereby sampling the output of said multiplexer at the end of said delay time for rendering the delay means effective on said gating means to gate the contents of said counter to said buffering means only if an input is supplied to said second input at the end of said delay time.
Claim 2
Dependent Claim
306 words
Data transferring circuitry including a keyboard with a plurality of keys and key actuated switches, buffing means for holding data corresponding to one of said keys and its associated switch, a multiplexer having an input connected to each of said switches and having a control set of inputs to which encoded data is supplied so as to provide an outpu when data supplied to the latter inputs correspond to one of said keys and key actuated switches, a counter providing a coded output on a plurality of output lines and connected to said control set of inputs, an oscillator for driving said counter, means connecting said multiplexer and said counter for stopping said counter when said multiplexer has an output, gating means for gating said counter to said buffering means so that, when said gating means is open, the contents of said counter is supplied to said buffering means, and delay means having a first input connected with the output of said multiplexer and having an output connected to said gating means to control the gating means and rendered operative when said multiplexer has an output applied to said first input to be effective after a predetermined delay time after thus being rendered operative for causing said gating means to open to gate the contents of said counter to said buffering means with said counter being stopped, said delay means including a second input connected to the output of said multiplexer and including means under control of a signal on said second input for thereby sampling the output of said multiplexer at the end of said delay time for rendering the delay means effective on said gating means to gate the contents of said counter to said buffering means only if an input is supplied to said second input at the end of said delay time.
Claim 3
Dependent Claim
123 words
Data transferring circuitry as set forth in claim 1, said delay means including first and second bi-stable devices and clocking means providing two timewise spaced clocking signals respectively applied to said first and second bi-stable devices for controlling these bi-stable devices, said first bi-stable device being under the control of the earlier one of said clocking signals and of a signal on said first input, said second bi-stable device being connected to said gating means to control the gating means and being controlled by the later one of said clocking signals, said sampling means including a control circuit connected to said second input of said delay means and also to the output of said first bi-stable device and controlling said second bi-stable device.
Claim 4
Dependent Claim
107 words
Data transferring circuitry as set forth in claim 2, said delay means including a third bi-stable device connected to said first input of said delay means and thereby to the output of said multiplexer and having its output connected to said first bi-stable device for controlling the latter, said clocking means including a decode driven by said oscillator and providing as outputs said clocking signal which are connected to said first and second bi-stable devices respectively, said control circuit for said second bi-stable device including an AND circuit connected with said second input of said delay means and also with the output of said first bi-stable device.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-07-22 | 1978-01-21 | 1978-07-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-07-22 | 1982-01-21 | 1982-07-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-07-22 | 1986-01-21 | 1986-07-23 | $7700.00 | Window Closed / Lapsed |