Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
183 words
Apparatus for recovering data from a composite signal having data bits comprised of pulses and zeros interleaved between clock pulses occurring at a predetermined frequency, comprising: a phase locked oscillator including a voltage controlled oscillator having a free running frequency of twice said predetermined frequency, means for comparing the output of said voltage controlled oscillator with said composite signal and means responsive to said comparison means for increasing the frequency of said voltage controlled oscillator whenever a pulse of said composite signal is advanced in time and for decreasing the frequency of said voltage controlled oscillator whenever a pulse of said composite signal is delayed in time; means for generating a data time window signal and a clock time window signal in response to the output signal of said voltage controlled oscillator; first gating means, said first gating means gating said composite signal in response to said data time window signal to produce a data output signal; and second gating means, said second gating means gating said composite signal in response to said clock time window signal to produce a clock output signal.
Claim 2
Dependent Claim
183 words
Apparatus for recovering data from a composite signal having data bits comprised of pulses and zeros interleaved between clock pulses occurring at a predetermined frequency, comprising: a phase locked oscillator including a voltage controlled oscillator having a free running frequency of twice said predetermined frequency, means for comparing the output of said voltage controlled oscillator with said composite signal and means responsive to said comparison means for increasing the frequency of said voltage controlled oscillator whenever a pulse of said composite signal is advanced in time and for decreasing the frequency of said voltage controlled oscillator whenever a pulse of said composite signal is delayed in time; means for generating a data time window signal and a clock time window signal in response to the output signal of said voltage controlled oscillator; first gating means, said first gating means gating said composite signal in response to said data time window signal to produce a data output signal; and second gating means, said second gating means gating said composite signal in response to said clock time window signal to produce a clock output signal.
Claim 3
Dependent Claim
158 words
Apparatus in accordance with claim 1 wherein said comparison means comprises a first circuit means, a second circuit means, and a summing circuit for summing the outputs of said first and second circuit means, and wherein said voltage controlled oscillator produces a square wave and a phase inverted square wave having free running frequencies of twice said predetermined frequency, said first circuit means producing a first polarity output to said summing circuit in response to detecting a pulse of said composite signal and a pulse of said square wave, said second circuit means producing a second polarity output opposite to that of said first polarity in response to detecting a pulse of said composite signal and a pulse of said inverted square wave. 3. Apparatus in accordance with claim 2 wherein said phase locked oscillator includes a pulse shaping circuit for shaping the pulses in said composite signal before applying them to said first and second circuit means.
Claim 4
Dependent Claim
73 words
Apparatus in accordance with claim 1 wherein said means for generating the data and clock time window signals includes a toggle flip-flop for generating two pulse signal outputs at frequencies equal to half of the frequency output of said voltage controlled oscillator, and a first and a second single shot circuit, said first and second single shot circuits being triggered in response to said two pulse signal outputs of said toggle flip-flop, respectively.
Claim 5
Dependent Claim
37 words
Apparatus in accordance with claim 4 including a logic circuit, said logic circuit causing said toggle flip-flop to skip an input pulse when said logic circuit detects an improper synchronization of data and clock pulses being recovered.
Claim 6
Dependent Claim
37 words
Apparatus in accordance with claim 5 wherein said logic circuit detects an improper synchronization by failing to detect a synchronization signal comprised of a predetermined number of zero data bits and a predetermined number of clock pulses.
Claim 7
Dependent Claim
21 words
Apparatus in accordance with claim 1 including means for delaying said composite signal applied to said first and second gating means.