Portable computer terminal using a standard television receiver

Claim 1

A data terminal for displaying lines of transmitted or received data characters on the screen of a conventional TV, the terminal comprising: first memory means for storing data characters equal in number to the character capacity of the screen; second memory means having its input connected to the first memory means for receiving one data line, at a time, from the first memory means; character generator means having its input connected to the output of the second memory means for converting each character of data in a line to a dot matrix representative of the character; means connecting the output of the character generator means to a signal mixer for generating a composite video data signal including horizontal and vertical synchronizing components which are introduced to the mixer; R.F. oscillator means connected to the output of the mixer for translating the frequency of the video signal to the R.F. region; means for connecting the translated video signal to the antenna of a conventional TV; the terminal further including control circuitry comprising: timing chain means connected in circuit with a phase lock loop for counting in a frequency stablized manner; means for generating a signal when a valid data character has been transmitted or received by the terminal; character address counter means connected to the signal generating means for incrementing its count in response to generated data valid signals; line address counter means having its input connected in circuit with the character address counter means for incrementing its count in response to the filling up of a data line with processed characters; means for connecting the outputs of the character and line address counter means to form a combined count; means for comparing the combined count with a count from the timing chain means and producing a comparison signal when an identity of counts exists therebetween; gate means for detecting coicidence between a comparison signal and a data valid signal; means connecting the output of the gate means to the first memory means for changing the mode of operation of the first memory means from recirculating to loading of data characters; load-recirculate means driven by the timing chain means and having an output connected to the second memory means for changing the mode of operation of the second memory means from recirculating to the loading thereof of a line of data characters from the first memory means; a high frequency clock line connected between the timing chain and the second memory means for reading out the characters stored therein to the character generating means; and means connected between the timing chain means and the character generator means for sequentially producing display trace signals for each row of the dot matrix of a character being fed to the character generator means by the second memory means.