Memory storage sequencer

Claim 2

An asynchronous main store sequencer (MSS) for processing information between a main memory store (MMS) and a central processing unit (CPU), buffer store (BS) and input output control unit (IOC), and for asynchronously resolving priority conflicts for MMS access among the CPU, BS and IOC units, said CPU, BS, or IOC being responsive to a common strobe signal, said MSS comprising: a. first signal means, coupled to said CPU, BS and IOC units, and responsive to said common strobe signal for simultaneously issuing Go signals which indicate a request for control of said MSS by the unit issuing the Go signal; b. variable delay line means coupled to said CPU, BS and IOC units for delaying by various predetermined amounts the Go signal issued by any or all of said CPU, BS or IOC units; c. priority resolving means in said MSS coupled to said variable delay line means, said priority resolving means responsive to the first Go signal received by said priority resolving means from one of said CPU, BS or IOC for assigning control of said MMS to the CPU, BS or IOC on a first-come-first-served basis; d. lockout means, coupled to said priority resolving means, for preventing higher priority units from obtaining control of said MSS until the controlling unit of said MMS terminates its processing.

Claim 3

An asynchronous main store sequencer (MSS) as recited in claim 1 wherein said MMS is comprised of a plurality of said MMS modules including module select means coupled to said priority resolving means for selecting one of said memory modules to communicate with one of said CPU, BS or IOC units having control of said MSS.

Claim 4

An asynchronous main store sequencer (MSS) as recited in claim 2 including first transmitter means coupled to said priority resolving means for transmitting the Go signal from said MSS to said MMS.

Claim 5

An asynchronous main store sequencer (MSS) as recited in claim 3 including first receiver means coupled to said first transmitter means for receiving the Go signal of said CPU, BS or IOC unit then having control of said MSS from said first transmitter means.

Claim 6

An asynchronous main store sequencer (MSS) as recited in claim 4 including lockout means coupled to said first receiver means, said lockout means responsive to the Go signal of the CPU, BS or IOC unit then having control of the MSS to prevent acceptance of a Go signal by said MSS of a CPU, BS or IOC which does not then have control of said MSS.

Claim 7

An asynchronous main store sequencer (MSS) as recited in claim 5 including acknowledge means coupled to said first receiver means and to said lockout means, for issuing an acknowledge signal to the MSS indicating receipt of the Go signal issued by the CPU, BS or IOC unit thus having control of the MSS.

Claim 8

An asynchronous main store sequencer (MSS) as recited in claim 6 including second receiver means coupled to said acknowledge means for receiving the acknowledge signal issued by said acknowledge means.

Claim 9

An asynchronous main store sequencer (MSS) as recited in claim 7 including current-memory-busy network coupled to said second receiver means and to said priority resolving means, said current-memory-busy network for issuing signals to said priority resolving network indicative of the current state of said MSS whereby said priority resolving means utilizes the information relative to the current state of said MMS to resolve priority conflicts among said CPU, BS and IOC units for control of said MSS.

Claim 10

An asynchronous main store sequencer (MSS) as recited in claim 8 includiNg information line means coupled to said MMS and to said CPU, BS and IOC units for reading or writing information out of or into said MMS from selected ones of said CPU, BS or IOC units.

Claim 11

An asynchronous main store sequencer (MSS) as recited in claim 9 including reservation line means coupled to said MSS and to said MMS for reserving the MMS for a selected one of said CPU, BS or IOC units for more than one MSS cycle.

Claim 12

An asynchronous main store sequencer (MSS) as recited in claim 10 including strobe means coupled to said MMS and to said MSS for issuing a strobe signal to said MSS indicating information is on said information lines and available from said MMS.

Claim 13

An asynchronous main store sequencer (MSS) as recited in claim 11 including storing means in said MSS coupled to said MMS and to said CPU, BS and IOC units, said storing means responsive to said strobe means and to a selected one of said CPU, BS or IOC unit for reading or writing information into or out of said MMS.

Claim 14

In combination with an asynchronous main store sequencer (MSS) a priority resolving network for resolving priority conflicts on a first-come-first-served basis among units competing for control of the MSS, said combination including a main memory store (MMS), a central processing unit (CPU), buffer store (BS), and input output control unit (IOC), said CPU, BS, or IOC being responsive to a common strobe signal, said MSS comprising: a. first signal means, coupled to said competing units, and responsive to said common strobe signal for simultaneously issuing Go signals which indicate a request for control of said MSS by the competing unit issuing the Go signal; b. variable delay line means coupled to said MSS and to said units competing for MSS control, said variable delay line means for delaying the Go signal issued by each of said units competing for MSS control; c. information line means coupled to said MSS and to said units competing for MSS control, said information line means for carrying data and control signals between said competing units and said MSS; d. competing-unit select means coupled to said delay line means, said MSS, and to each of said units competing for MSS control, said select means responsive to selected signals on said information line means and to signals indicative of the state of the competing units, the state of the MSS and the first received Go signal by the MSS for selecting one of said competing units to acquire control of the MSS; e. lockout means, coupled to said priority resolving means, for preventing higher priority units from obtaining control of said MSS until the controlling unit of said MMS terminates its processing.

Claim 15

In combination with an asynchronous main store sequencer (MSS) a priority resolving network for resolving priority conflicts on a first-come-first-served basis among units competing for control of the MSS, said combination including a main memory store (MMS), a central processing unit (CPU), buffer store (BS), and input output control unit (IOC), said CPU, BS, or IOC being responsive to a common strobe signal, said MSS comprising: a. first signal means, coupled to said competing units, and responsive to said common strobe signal for simultaneously issuing Go signals which indicate a request for control of said MSS by the competing unit issuing the Go signal; b. variable delay line means coupled to said MSS and to said units competing for MSS control, said variable delay line means for delaying the Go signal issued by each of said units competing for MSS control; c. information line means coupled to said MSS and to said units competing for MSS control, said information line means for carrying data and control signals between said competing units and said MSS; d. competing-unit select means coupled to said delay line means, said MSS, and to each of said units competing for MSS control, said select means responsive to selected signals on said information line means and to signals indicative of the state of the competing units, the state of the MSS and the first received Go signal by the MSS for selecting one of said competing units to acquire control of the MSS; e. lockout means, coupled to said priority resolving means, for preventing higher priority units from obtaining control of said MSS until the controlling unit of said MMS terminates its processing.

Claim 16

The combination as recited in claim 13 wherein said combination includes a main memory store (MMS) having a plurality of memory modes and further including MMS select means coupled to said variable delay line means, said MMS select means responsive to signals from selected ones of said information line means, and to the Go signal of the competing unit then in control of the MSS, said MMS select means for selecting the MMS module to be accessed by the competing unit then in control of the MSS.

Claim 17

The combination as recited in claim 14 including assignment flag means coupled to said MMS and the said MSS and responsive to signals on selected ones of said information line means, said assignment flag means for generating signals indicative of the state of said MMS.

Claim 18

The combination as recited in claim 15 including blocking means coupled to said MMS and said MSS, and responsive to signals on selected ones of said information line means and to signals indicative of the state of said MMS, said blocking means for preventing access to said MSS by competing units not then in control of said MSS.