Data processing system

Claim 2

A data unit adapted for connection to a multiple conductor bus in a data processing system, the data processing system having means for transmitting address signals, cycle control signals indicating the direction of a data transfer and a delayed first synchronization signal onto corresponding bus conductors to produce in said data unit at least one type of data unit cycle for transferring data between bus data conductors and said data unit during a transfer interval, said data unit comprising: A. at least one data storage location with each said location having a unique address, B. selection means for generating a data unit selection signal in response to address signals on the address conductors which identify any storage location in said data unit, C. means for performing a data unit cycle during a transfer interval, D. means connected to said data unit cycle performing means and responsive to the cycle control signals for controlling the type of data unit cycle that is performed, E. coincidence means connected to said data unit cycle performing means and responsive to the coincidence of a delayed first synchronization signal and a data unit selection signal to initiate a data unit cycle, and F. means responsive to said coincidence means for generating a second synchronization signal indicative of the completion of a data unit cycle and responsive to a subsequent termination of the delayed first synchronization signal for terminating the second synchronization signal.

Claim 3

A data unit as recited in claim 1 comprising a sEt of data storage locations with an ordered sequence of addresses, said selection means additionally including an address decoder responsive to the address signals for selecting a specified one of said data storage location for the data unit cycle.

Claim 4

A data unit as recited in claim 1 wherein said second synchronizing signal generating means includes a delay circuit responsive to the initiation of a data unit cycle by said coincidence means.

Claim 5

A data unit as recited in claim 1 wherein said cycle control signals indicate a transfer into an identified one of said storage locations from the data conductors during the transfer interval, said second synchronization signal generating means producing the second synchronization signal to indicate the storage of the data in the identified location by said data unit cycle performing means.

Claim 6

A data unit as recited in claim 1 wherein said cycle control signals indicate a transfer from an identified one of said locations onto the data conductors during the transfer interval, said second synchronization signal generating means producing the second synchronization signal to indicate that data from the identified location has been placed on the data conductors by said data unit cycle performing means.

Claim 7

A peripheral unit adapted for controlling a data transfer with another unit in a data processing system in which the peripheral units have relative priorities in the system, the system including a priority element adapted for connection to a data processing system bus having data, address and control conductor means, said peripheral unit comprising: A. request means for transmitting a request signal onto request control conductor means when said peripheral unit is prepared to control a data transfer, B. acknowledgement means responsive to the coincidence of a request signal from said request means and the receipt of a granting signal from the priority element on a granting control conductor means by transmitting an acknowledgement signal onto an acknowledgement control conductor means, said request means terminating the request signal in response to the acknowledgement signal, C. interval indicating means responsive to the coincidence of an acknowledgement signal and the absence of a busy signal on a busy control conductor means by indicating an interval during which said peripheral unit can transfer data, D. busy signal generating means responsive to said interval indicating means for transmitting a busy signal onto the busy control conductor means, said acknowledgement signal transmitting means terminating the acknowledgement signal in response to the busy signal generating means, and E. means responsive to said busy signal generating means for controlling a data transfer over the data conductor means between the peripheral unit and another unit connected to the system bus, said busy signal generating means terminating the busy signal on completion of the data transfer operation to indicate the end of the data transfer interval.

Claim 8

A peripheral unit adapted for controlling a data transfer with another unit in a data processing system in which the peripheral units have relative priorities in the system, the system including a priority element adapted for connection to a data processing system bus having data, address and control conductor means, said peripheral unit comprising: A. request means for transmitting a request signal onto request control conductor means when said peripheral unit is prepared to control a data transfer, B. acknowledgement means responsive to the coincidence of a request signal from said request means and the receipt of a granting signal from the priority element on a granting control conductor means by transmitting an acknowledgement signal onto an acknowledgement control conductor means, said request means terminating the request signal in response to the acknowledgement signal, C. interval indicating means responsive to the coincidence of an acknowledgement signal and the absence of a busy signal on a busy control conductor means by indicating an interval during which said peripheral unit can transfer data, D. busy signal generating means responsive to said interval indicating means for transmitting a busy signal onto the busy control conductor means, said acknowledgement signal transmitting means terminating the acknowledgement signal in response to the busy signal generating means, and E. means responsive to said busy signal generating means for controlling a data transfer over the data conductor means between the peripheral unit and another unit connected to the system bus, said busy signal generating means terminating the busy signal on completion of the data transfer operation to indicate the end of the data transfer interval.

Claim 9

A peripheral unit as recited in claim 6 wherein said data transfer control means includes: i. means for generating address signals onto the address conductor means for another unit in the system, ii. means for generating cycle control signals onto cycle control conductor means indicating the direction of a data transfer, and iii. means for generating a delayed first synchronizing signal onto first synchronization control conductor means, the signal initiating a data unit cycle in the other unit to thereby effect the transfer during the data transfer interval.

Claim 10

A peripheral unit as recited in claim 6 wherein the data processing system additionally comprises a processor unit connected to the system bus, said peripheral unit additionally including a circuit enabled in response to certain requests for effecting a transfer of data directly to the processor, said circuit comprising i. means for transmitting a digital word onto the data conDuctors, ii. means responsive to said busy signal generating means for transmitting an interruption signal onto interrupt control conductor means, the processor unit accepting the digital word in response to the interrupt signal and sending a second synchronization signal onto second synchronization control conductor means for indicating the receipt of the digital word, and iii. means responsive to the second synchronization signal for disabling said interruption signal transmitting means, said digital word transmitting means and said busy signal generating means.

Claim 11

A peripheral unit as recited in claim 6 additionally comprising: A. non-processor request means for transmitting a non-processor request onto non-processor request control conductor means, and B. means responsive to said non-processor request means and to a signal granting the non-processor request appearing on non-processor granting control conductor means for enabling said acknowledgement means, said busy signal generating means and said data transfer control means to effect a data transfer with another unit connected to the bus, said data transfer control means including means for transmitting address signals onto the address conductor means to identify the other unit to be involved in the transfer.

Claim 12

A peripheral unit as recited in claim 9 wherein said data transfer control means additionally comprises: A. means for transmitting a delayed first synchronization signal onto first synchronization control conductor means indicating the initiation of a data transfer cycle, the other unit including means for effecting a data unit cycle in response thereto and generating a second synchronization signal onto second synchronization control conductor means indicating the completion of the data unit cycle, B. means responsive to the receipt of the second synchronization signal disabling said delayed first synchronization transmitting means, the other unit thereby terminating its second synchronization signal, and C. means responsive to the termination of the second synchronization signal for disabling said busy signal generating means to thereby terminate the data transfer interval.