US3815033A
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Discrete adaptive delta modulation system
Assignee: AT&T Inc
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Filing: 1972-06-01
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Granted: 1974-06-04
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Expires: 1992-06-01
Abstract
Abstract In a discrete adaptive delta modulation system, the modulator located at the transmitter converts an analog signal into a digital signal at the rate fs while the demodulator located at the receiver converts the digital signal back into the analog signal. The modulator and demodulator each comprise a programmable pulse generator operating at the rate ft for providing a controlled number of pulses k during each sampling period 1/fs to its associated single stepsize analog integrator. The modulator further comprises a comparator, a quantizer, and a sampling pulse generator operating at the rate fs while the demodulator further comprises a low-pass filter in series with the integrator. The number of pulses k provided by the programmable pulse generator multiplied by the integrator basic stepsize sigma o determines the overall stepsize sigma k in the integrator output signal, where k ft/fs. A feature of this system is that the number n of available stepsizes sigma k, which is a function of the ratio of generator rates ft and fs, can be several hundred without affecting the complexity of the integrating circuitry.
Inventors
- 👤 S Tewksbury
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 10:24
CPC Classifications
H; H03; H03M; H03M3/00; H03M3/02; H03M3/022
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
90 words
A delta modulating system wherein a delta modulated digital signal at the rate fs corresponds to an analog signal, a demodulator for said system comprising: means for generating pulses at the rate ft greater than or equal to fs, means for generating sampling pulses at the rate fs means jointly responsive to said digital signal and said sampling pulses at the rate fs for producing a retimed signal, and integrating means jointly responsive to said retimed signal and to said pulses at the rate ft for reconstructing said analog signal.
Claim 2
Dependent Claim
90 words
A delta modulating system wherein a delta modulated digital signal at the rate fs corresponds to an analog signal, a demodulator for said system comprising: means for generating pulses at the rate ft greater than or equal to fs, means for generating sampling pulses at the rate fs means jointly responsive to said digital signal and said sampling pulses at the rate fs for producing a retimed signal, and integrating means jointly responsive to said retimed signal and to said pulses at the rate ft for reconstructing said analog signal.
Claim 3
Dependent Claim
50 words
The demodulator of claim 1 wherein said retimed signal producing means is a two-level quantizer which at the rate fs emits a first output pulse when said digital signal is at one binary level and emits a second output pulse when said digital signal is at a second binary level.
Claim 4
Dependent Claim
12 words
The demodulator of claim 2 wherein said two-level quantizer is a flip-flop.
Claim 5
Dependent Claim
21 words
The demodulator of claim 1 wherein said means for generating pulses at the rate ft is responsive to said retimed signal.
Claim 6
Dependent Claim
59 words
The demodulator of claim 1 wherein said integrating means is a single stepsize analog integrator having the basic stepsize sigma O and wherein amplitude changes sigma k in said reconstructed analog signal during any sampling interval 1/fs are given by the product of sigma O and the number of pulses k applied at the rate ft to said integrator.
Claim 7
Dependent Claim
16 words
The demodulator of claim 5 wherein said single stepsize analog integrator is a charge parcelling integrator.
Claim 8
Dependent Claim
28 words
The demodulator of claim 1 wherein said means for generating pulses at the rate ft is responsive to said means for generating sampling pulses at the rate fs.
Claim 9
Dependent Claim
86 words
The demodulator of claim 5 wherein said means for generating pulses at the rate ft includes: counting means, adaption logic responsive to said digital signal for controlling the count of said counting means, a clock source for generating pulses at the constant rate ft max greater than or equal to ft, and pulse rate selecting means jointly responsive to said clock source and said counting means for emitting at the rate ft said number of pulses k numerically equal to the count of said counting means.
Claim 10
Dependent Claim
34 words
The demodulator of claim 8 wherein said pulse rate selecting means is a binary rate multiplier for producing during the sampling interval 1/fs said k pulses ranging in number from 1 to ft max/fs.
Claim 11
Dependent Claim
25 words
The demodulator of claim 8 wherein said counting means is a binary counter whose count varies from 1 to ft max/fs in powers of 2.
Claim 12
Dependent Claim
134 words
The demodulator of claim 5 wherein said means for generating pulses at the rate ft includes: counting means, adaption logic for controlling the count of said counting means, a clock source for generating pulses at the constant rate ft max greater than or equal to ft, and pulse rate selecting means jointly responsive to said clock source and said counting means for emitting at the rate ft said number of pulses k numerically to the count of said counting means; and wherein said demodulator further comprises: means responsive to said clock source for generating pulses at the rate fs, and means jointly responsive to said digital signal and said sampling pulses at the rate fs for producing a retimed signal; said adaption logic and said integrating means both being responsive to said retimed signal.
Claim 13
Dependent Claim
22 words
The demodulator of claim 1 wherein said means for generating sampling pulses at the rate fs is responsive to said retimed signal.
Claim 14
Dependent Claim
140 words
The demodulator of claim 12 wherein said integrating means is a single step-size analog integrator having the basic stepsize sigma O and wherein amplitude changes sigma k in said reconstructed analog signal during any sampling interval 1/fs are given by the product sigma O and the number of pulses k applied at the rate ft to said integrator; and wherein said means for generating sampling pulses at the rate fs includes: counting means, adaption logic responsive to said retimed signal for controlling the count of said counting means, a clock source for generating pulses at the constant rate fs max greater than or equal to fs, and pulse rate selecting means jointly controlled by said clock source and said counting means for emitting at the rate fs a plurality of pulses numerically equal to the count of said counting means.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-06-03 | 1977-12-03 | 1978-06-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-06-03 | 1981-12-03 | 1982-06-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-06-03 | 1985-12-03 | 1986-06-04 | $7700.00 | Window Closed / Lapsed |