US3812470A
Expired / Lapsed
US
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Programmable digital signal processor
Assignee: Westinghouse Electric Corp
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Filing: 1972-07-31
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Granted: 1974-05-21
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Expires: 1992-07-31
Abstract
Abstract A programmable digital signal processor using microprogrammed macro instructions to perform complex arithmetic instructions and other complex data processing instructions is disclosed. A plurality of address counters and memory modules are included to permit the generation of address sequences which simplify the implementation of complex macro instructions. A number representation scheme is used which simplifies the handling of overflows which occur during certain types of statistical problems. A typical example of a macro instruction utilizing these features is a Fast Fourier Transform.
Inventors
- 👤 J Murtha
- 👤 J Ross
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 17:39
CPC Classifications
G; G06; G06F; G06F17/00; G06F17/10
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
101 words
A programmable digital processor comprising: a. an arithmetic unit for processing at least two digital data signals including logic to detect any overflow which result from an arithmetic operation on said data signals, said logic including means for setting the magnitude of the output signal of the arithmetic unit to its maximum value when an overflow occurs; b. memory means for storing digital program words specifying the sequence of operation to be performed by said arithmetic unit; and c. control means for reading and decoding said program words and for generating in response thereto control signals to control said arithmetic unit.
Claim 2
Dependent Claim
101 words
A programmable digital processor comprising: a. an arithmetic unit for processing at least two digital data signals including logic to detect any overflow which result from an arithmetic operation on said data signals, said logic including means for setting the magnitude of the output signal of the arithmetic unit to its maximum value when an overflow occurs; b. memory means for storing digital program words specifying the sequence of operation to be performed by said arithmetic unit; and c. control means for reading and decoding said program words and for generating in response thereto control signals to control said arithmetic unit.
Claim 3
Dependent Claim
40 words
A programmable digital processor in accordance with claim 1 wherein said memory means includes a plurality of independently accessible memory elements in which said digital program words and data signals to be processed by said arithmetic unit may be stored.
Claim 4
Dependent Claim
26 words
A programmable digital processor in accordance with claim 2 further including a plurality of address counters which can be used to selectively address said memory elements.
Claim 5
Dependent Claim
24 words
A programmable digital processor in accordance with claim 3 further including micro program means for selectively coupling said address counters to said memory elements.
Claim 6
Dependent Claim
28 words
A programmable digital processor in accordance with claim 3 wherein said at least one of said address counters is adapted to generate address sequences in reverse bit order.
Claim 7
Dependent Claim
22 words
A programmable digital processor in accordance with claim 5 further including means coupled to said address counters for determining the address sequence.
Claim 8
Dependent Claim
33 words
A programmable digital processor in accordance with claim 1 wherein said data signals are digital representation of complex numbers, said arithmetic uniT processing the real and complex components of said data signals independently.
Claim 9
Dependent Claim
68 words
A programmable digital processor in accordance with claim 7 wherein an overflow generated by processing the real component of said data signals causes the associated real component of the output of said arithmetic unit to be set to a value equal to the maximum magnitude which can be represented and wherein the imaginary components or the output signal of said arithmetic unit are not effected by said overflow.
Claim 10
Dependent Claim
69 words
A programmable digital processor in accordance with claim 7 wherein an overflow generated by processing the imaginary component of said data data signals causes the associated imaginary component of the output or said arithmetic unit to be set to a value equal to the maximum magnitude which can be represented and wherein the real components or the output signal or said arithmetic unit are not effected by said overflow.
Claim 11
Dependent Claim
31 words
A programmable processor in accordance with claim 1 further including a counter coupled to said arithmetic unit such that said counter is incremented each time an arithmetic operation generates an overflow.
Claim 12
Dependent Claim
18 words
A programmable digital processor in accordance with claim 1 wherein said digital program words are macro program words.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-05-20 | 1977-11-19 | 1978-05-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-05-20 | 1981-11-19 | 1982-05-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-05-20 | 1985-11-19 | 1986-05-21 | $7700.00 | Window Closed / Lapsed |