Programmable matrix controller

Claim 2

A controller comprising: a memory matrix operable to store a plurality of binary words and including means to selectively read said words; a logic input bus; a plurality of input circuits, each input circuit being operable to receive a condition signal from an external device and generate said condition signal to the logic input bus when it is addressed; a logic output bus; a plurality of output circuits connected to the logic output bus, each output circuit being operable to actuate an external device in response to a command signal on said logic output bus when it is addressed; an address decoder connected to said memory matrix to receive an address code in each word read from said memory matrix and being operable in response thereto to selectively address an input or output circuit by generating an activate signal thereto; and a central logic unit having first and second storage means connected to said memory matrix to receive four distinct operation signals read from said memory matrix, said central logic unit also being connected to said logic input and logic output buses; wherein said central logic unit is operable in response to a received operation signal said operation signals to perform one of said four distinct associated operations; said associated operations including not more than the following four distinct operations, (1) examine the condition of an external device connected to an addressed input circuit and store the result in said first storage means, (2) examine the condition of an external device connected to an addressed input circuit and store the inversion of the result in said first storage means, (3) shift the results stored in said first storage means to said second storage means, and (4) generate a command signal to said logic output bus which is responsive to the results stored in both storage means.

Claim 3

The controller as recited in claim 1 in which said central logic unit includes an output logic gate connected to said logic output bus, and wherein said first storage means is a first flip-flop connected to said logic input bus, and said second storage means is a second flip-flop connected to said first flip-flop, and in which an output terminal on each of said flip-flops connects to said output logic gate.

Claim 4

The controller as recited in claim 2, which includes: a BRT bus; a SET bus; and an operation decoder connected to said memory matrix to receive operation codes and selectively generate in response thereto an operation signal to the BRT bus and an operation signal to the SET bus; wherein said BRT bus is connected to said first flip-flop and to said second flip-flop, and said SET bus is connected to said first flip-flop and said second flip-flop.

Claim 5

The controller as recited in claim 3, which includes: an XIO bus; and a second logic gate connected between said logic input bus and said first flip-flop, wherein said operation decoder selectively generates an operation signal to said XIO bus in response to operation codes received from said memory matrix, and wherein said XIO bus is connected to said second logic gate.

Claim 6

The controller as recited in claim 1, in which each output circuit includes a flip-flop and a logic gate, wherein said flip-flop has an output terminAl connected to said logic gate, an output terminal connectable to an external device, an input terminal connected to said logic output bus, and a clock terminal connected to receive an activate signal from said address decoder; and wherein said logic gate has an input terminal connected to receive an activate signal from said address decoder and an output terminal connected to said logic input bus.

Claim 7

The controller as recited in claim 5, which includes a SET bus and an operation decoder connected to said memory matrix to receive an operation code and generate in response thereto an operation signal to the SET bus, wherein said SET bus is connected to the clock terminals on said output circuit flip-flops.

Claim 8

The controller as recited in claim 1 wherein said logic input bus contains not more than one electrical conductor.

Claim 9

A controller comprising: a memory operable to store a set of binary words and including means for selectively reading said binary words; a plurality of input circuits; an output circuit; a logic input line connected to said input circuits; a logic output line connected to said output circuit; an address decoder connected to said memory, connected to said output circuit, and connected to said input circuits; and a central logic unit connected to said memory, connected to said logic input line, and connected to said logic output line, said central logic unit having first and second storage means connected to receive operation signals from said memory and in response thereto selectively perform one of the following operations: read and store in said first storage means the condition of said logic input line, shift and store in said second storage means the stored result of a read operation, and generate a digital signal to said output circuit which is responsive to the results stored in said first and second storage means.

Claim 10

A controller comprising: a memory operable to store a set of binary words and including means for selectively reading said binary words; a plurality of input circuits; an output circuit; a logic input line connected to said input circuits; a logic output line connected to said output circuit; an address decoder connected to said memory, connected to said output circuit, and connected to said input circuits; and a central logic unit connected to said memory, connected to said logic input line, and connected to said logic output line, said central logic unit having first and second storage means connected to receive operation signals from said memory and in response thereto selectively perform one of the following operations: read and store in said first storage means the condition of said logic input line, shift and store in said second storage means the stored result of a read operation, and generate a digital signal to said output circuit which is responsive to the results stored in said first and second storage means.

Claim 11

The controller as recited in claim 8 in which said first storage means is connected to said logic input line and to said memory, and in which said read and store operation is performed when a read operation signal is read from said memory to said central logic unit and one of said input circuits is addressed by said address decoder.

Claim 12

The controller as recited in claim 9 in which said first storage means is a flip-flop which is stable in either a first logic state or a second logic state, wherein the condition of said logic input line is applied to said first flip-flop when said read and store operation signal is generated, and wherein said first flip-flop is driven to one of its logic states by the logic state of said logic input line during the read operation.

Claim 13

The controller as recited in claim 9 in which said said second storage means is connected to both said first storage means and to said memory, and wherein said shift and store operation is performed when a BRT operation signal is read from memory to said second storage means.

Claim 14

The controller as recited in claim 10 in which said second storage means is a flip-flop connected to said first flip-flop and connected to receive a BRT operation signal from said memory, and wherein the logic state of said first flip-flop is shifted to said second flip-flop when the BRT operation signal is read from memory.

Claim 15

The controller as recited in claim 11 in which said central logic unit includes an output logic gate having a first input terminal connected to said first storage means, a second input terminal connected to said second storage means, and an output terminal connected to said logic output line.

Claim 16

The controller as recited in claim 12 in which said central logic unit includes an output OR gate having a first input terminal connected to said first flip-flop, a second input terminal connected to said second flip-flop, and an output terminal connected to said logic output line.

Claim 17

The controller as recited in claim 13 in which the memory connects to said output circuit through a SET bus, said SET bus connects to said first and second storage means, and said central logic unit operates to generate a digital signal to said output circuit when an operation signal is generated on said SET bus and said output circuit is addressed by said address decoder.

Claim 18

The controller as recited in claim 14 in which said output circuit connects with said memory and the logic state generated on said logic output line by said central logic unit is applied to said output circuit when a SET operation signal is received.

Claim 19

The controller as recited in claim 16 in which said SET operation signal is applied to said first and second flip-flops in said central logic unit to drive each into one of its two logic states.

Claim 20

A controller comprising: a memory operable to store a set of binary words and including means for selectively reading said binary words; a plurality of input circuits; a logic input bus connected to said input circuits; a logic output bus; an address decoder connected to said memory and connected to said input circuits; an operation decoder connected to receive not more than two bits from each word read from memory and in response thereto generate a set of operation signals; a central logic unit connected to said operation decoder, connected to said logic input bus, and connected to said logic output bus, said central logic unit being responsive to said operation signals received from said operation decoder to selectively perform one of the following operations: read and store the condition of said logic input bus, shift and store the result of a previous read operation, and generate a digital signal to said logic output bus which is responsive to the stored results; and an output circuit which includes, a flip-flop connected to said logic output bus and to said address decoder, wherein the state of said flip-flop is determined by the logic signal generated on said logic output bus when the output circuit is addressed by said address decoder.

Claim 21

A controller comprising: a memory operable to store a set of binary words and including means for selectively reading said binary words; a plurality of input circuits; a logic input bus connected to said input circuits; a logic output bus; an address decoder connected to said memory and connected to said input circuits; an operation decoder connected to receive not more than two bits from each word read from memory and in response thereto generate a set of operation signals; a central logic unit connected to said operation decoder, connected to said logic input bus, and connected to said logic output bus, said central logic unit being responsive to said operation signals received from said operation decoder to selectively perform one of the following operations: read and store the condition of said logic input bus, shift and store the result of a previous read operation, and generate a digital signal to said logic output bus which is responsive to the stored results; and an output circuit which includes, a flip-flop connected to said logic output bus and to said address decoder, wherein the state of said flip-flop is determined by the logic signal generated on said logic output bus when the output circuit is addressed by said address decoder.

Claim 22

The controller as recited in claim 18 in which said output circuit is connected to receive a SET operation signal from said operation decoder and said output circuit includes a logic gate having a first input terminal connected to said address decoder, a second input terminal connected to said flip-flop, and an output terminal connected to said logic input bus.

Claim 23

The controller as recited in claim 19 in which said output circuit flip-flop is connected to receive said SET operation signal and said flip-flop and said logic gate are connected to said address decoder to be addressed together, wherein the state of said flip-flop is determined by the logic state of said logic output bus only when the output circuit is addressed by said address decoder and said SET operation signal is simultaneously received from said operation decoder.

Claim 24

A controller which comprises: a memory containing a set of instructions, each instruction including a two-bit operation code and an address code, said memory including means for selectively reading said instructions; an output circuit; a plurality of input circuits, each input circuit having an input terminal and an output terminal, and each input circuit being operable to test the condition of an input device connected to its input terminal and to generate a corresponding logic signal at its output terminal; a logic input bus connected to the output terminal of each input circuit; an address decoder connected to receive the address code in each instruction read from memory and in response thereto address one of said input or output circuits by generating an activate signal thereto; an operation decoder connected to receive the two-bit operation code in each instruction read from memory, and in response thereto generate one of four separate operation signals wherein said operation signals are each associated with an operation to be performed; and a central logic unit which includes a First flip-flop connected to said operation decoder, connected to said output circuit and connected to said logic input bus, and a second flip-flop connected to said operation decoder, to said output circuit and to said first flip-flop, wherein said central logic unit is responsive to said one of said operation signals to perform one of the following said operations, (1) store the logic signal generated by an addressed input circuit in said first flip-flop, (2) store the inversion of the logic signal generated by an addressed input circuit in said first flip-flop (3) shift the logic state stored in said first flip-flop to said second flip-flop, and (4) generate a command signal to said output circuit, the logic state of which is determined by the logic state of said first and second flip-flops.

Claim 25

A controller which comprises: a memory containing a set of instructions, each instruction including a two-bit operation code and an address code, said memory including means for selectively reading said instructions; an output circuit; a plurality of input circuits, each input circuit having an input terminal and an output terminal, and each input circuit being operable to test the condition of an input device connected to its input terminal and to generate a corresponding logic signal at its output terminal; a logic input bus connected to the output terminal of each input circuit; an address decoder connected to receive the address code in each instruction read from memory and in response thereto address one of said input or output circuits by generating an activate signal thereto; an operation decoder connected to receive the two-bit operation code in each instruction read from memory, and in response thereto generate one of four separate operation signals wherein said operation signals are each associated with an operation to be performed; and a central logic unit which includes a First flip-flop connected to said operation decoder, connected to said output circuit and connected to said logic input bus, and a second flip-flop connected to said operation decoder, to said output circuit and to said first flip-flop, wherein said central logic unit is responsive to said one of said operation signals to perform one of the following said operations, (1) store the logic signal generated by an addressed input circuit in said first flip-flop, (2) store the inversion of the logic signal generated by an addressed input circuit in said first flip-flop (3) shift the logic state stored in said first flip-flop to said second flip-flop, and (4) generate a command signal to said output circuit, the logic state of which is determined by the logic state of said first and second flip-flops.

Claim 26

The controller as recited in claim 21 in which the input circuits are connected to said central logic unit by a logic input bus comprised of a single electrical conductor.