Computer input-output system

Claim 2

In a general purpose digital computer having a central processing unit performing arithmetic operations on data in accordance with instructions, signals representing the instructions and the data are stored as information in a memory having a plurality of individually addressable memory locations, the computer further having a plurality of peripheral devices for input-output operations of information to be fed to memory and/or to be withdrawn therefrom, the improvement comprising: a plurality of device controllers each for controlling at least one of the devices of the plurality, for the providing or receiving of data, each device controller including generator means for providing an interrupt call signal; a plurality of input-output processors each connected for controlling transmission of data between a subplurality of device controllers of the plurality and memory; a plurality of first connection means, one for each subplurality of device controllers and respectively connected to all of the respective generator means of the respective subplurality of device controllers for receiving call signals therefrom and providing a single call signal to the respective processor independently from the number of generator means having produced a call signal; second connection means connecting the first conection means of the plurality to a single line leading to the central processing unit, to provide a single interrupt request signal if one or more of the generator means provides a call signal; first means in the central processing unit responsive to an interrupt request when received via said line and causing the central processing unit to execute a particular instruction thereby causing interrogating signals to be provided to the input-output processors; third connection means, interconnecting the input-output processors of the plurality for establishing a priority ranking among them, the input-output processors including means to respond to the interrogating signals from the central processing unit if the respective input-output processor has highest priority rank among those which received a call signal, and to transmit second interrogating signals to the device controllers of the respective subplurality; second means interconnecting the device controllers of each of the subpluralities for establishing a priority ranking among the device controllers of each of the subpluralities, in that any device controller of the subplurality will transmit one of the second interrogating signals to the device controller of next lower priority only when it has not provided an interrupt call, the particular one of the device controllers responding to the second interrogating signals having highest priority rank among those having provided interrupt calls at the time of the second interrogating signals, said particular device controller not transmitting the one second interrogating signal to the device controller of next lower priority ranking; third means in each device controller for providing an identifying code to the respective input-output processor when having responded to the second interrogating signals by operation of the second means to identify the device that requested the interrupt; and fourth means in each input-output processor for receiving said code and to cause transmission of said code and of its own identifying code to the central processor.

Claim 3

The improvement as set forth in claim 1, the fourth means including fifth means for transferring said codes to a particular memory location for withdrawal therefrom by the central processing unit; and sixth means in each processor for providing a response signal to the central processing unit via a line common to all processors.

Claim 4

The improvement as set forth in claim 1, comprising a plurality of pairs of lines, the lines of a pair connected to the devices of a subplurality and to the respective processor; a pair of condition code lines connected to all processors and to the central processing unit; means in each input output processor for receiving signals on the pair of lines connected to the devices of the respective subplurality, the processor having responded to the first interrogation signals passing the signals to the pair of condition code lines; and means in each device controller for controlling the lines of the respective pair when having responded by operation of the second means to provide the identification code, to provide a representation of recognition of placement and of the type of an interrupt call.

Claim 5

The improvement as set forth in claim 1, the processors each including a plurality of interrupt status indicators representing different causes for interrupt calls as provided by the device controllers controlled by the respective processors, the indicators being included in the information returned by an input-output processor of the plurality under control of the fourth means.

Claim 6

The improvement as set forth in claim 1, the second means including, in each device controller, a signal receiver and a priority control signal driver providing a priority control signal as the one second interrogating signal to the signal receiver of the device controller of next lower priority rank, the receiver of the device controller of highest priority rank receiving an independently developed priority control signal; and means in each device controller responsive to particular conditions in the device controller requiring connection of the respective device controller to the processor and which when receiving a priority control signal through its receiver, establishes the operative connection while inhibiting the providing of a priority control signal by its driver, the particular condition including the placing of an interrupt call to said single call line by the respective device controller.

Claim 7

In a general purpose digital computer as in claim 1, said means for establishing a priority rank for each input-output processor of the plurality for connection to the central processing unit, including in each of the processors, first control means for receiving an interrogating signal from the central processing unit and second control means for passing the interrogating signals respectively to the first control means of next lower priority rank, the input-output processor of highest priority rank connected to receive the interrogating signal directly from the central processing unit; and a plurality of receiving means respectively included in said processors, each receiving means responsive to particular first conditions including an interrupt call signal from one of the device controllers as cooperating with the respective processor, requiring connection of the respective processor to the central processing unit and providing the operative connection to the central processing unit when the respective first control means receive the priority control signal while inhibiting operation of the respective second control means.

Claim 8

The improvement set forth in claim 6, each input-output processor including third control means for receiving a return response signal from a processor of next lower priority rank; each processor including fourth control means for passing a return response signal to the processor of next higher priority in response to a return response signal when received by the third control means from the processor of respective next lower priority rank, the fourth control means of each processor producing a return response signal in response to the interrogation signal if received by its first control means, if the respective processor is the one of highest priority among those requiring communication with the central processing unit, including a request for an interrupt pursuant to an interrupt call by one of the respective device controllers connected to the respective processor; and the third means of the highest priority rank processor providing the respective return response to the central processing unit.

Claim 9

In a general purpose digital computer having a central processing unit performing arithmetic operation on data in accordance with instructions, signals representing the instruction and the data are stored as information in a memory having a plurality of individually addressable memory locations, the computer further having a plurality of peripheral devices for input-output operations of information to be fed to memory and/or to be withdrawn therefrom, the improvement comprising: a plurality of device controllers each for controlling at least one of the devices of the plurality, for the providing or receiving of data; an input-output processor connected for controlling transmission of data between the device controllers and memory; interface connecting means between the input-output processor and the device controllers including data lines and an interrupt call line, for the transfer of an interrupt call signal between device controllers and processor, there being means in the input-output processor for transmitting the call signal as interrupt request to the central processing unit for interrupting the operation thereof; first circuit means in the processor connected to obtain transfer of data between the processor and either one of the device controllers of the plurality through said interface connecting means; a plurality of flag means in the input-output processor including, a first flag means being in the set or reset state if an interrupt request signalled to the central processing unit or not, at a first operative condition of a device controller of the plurality when cooperating with the processor, and when signalling such first condition to the input-output processor, such first condition representing that the device controller and the respective device must terminate the reception or providing of data; the flag means of the plurality including second flag means being in the set or reset state if an interrupt request is to be signalled to the central processing unit or not at a second operative condition of the input-output processor, the second operative condition representing completion of data transfer between the cooperating device controller of the plurality and the memory via the input-output processor; first means in each of the device controllers including means (a) responsive to the state of device operation to provide a signal representing the first operative condition and means (b) for signaling the first operative condition to the input-output processor when cooperating therewith and through said interface connecting means; second means in the input-output processor alternatively responsive to signaling of the first condition in association with the state of the first flag means or to the existence of the second condition in association with the state of the second flag means for providing a particular order through the data lines of said interface connection to the device controller of the plurality, said particular order signaling to the device controller to request and interrupt; and an interrupt call generator in each of the device controllers responsive to an interrupt order when received from the input-output processor by operation of the second means to provide an interRupt call to said interrupt call line for transmission as interrupt request to the central processing unit, the central processing unit including third means responsive to such an interrupt request for interrupting the operation of the central processing unit then performed on data.

Claim 10

In a general purpose digital computer having a central processing unit performing arithmetic operation on data in accordance with instructions, signals representing the instruction and the data are stored as information in a memory having a plurality of individually addressable memory locations, the computer further having a plurality of peripheral devices for input-output operations of information to be fed to memory and/or to be withdrawn therefrom, the improvement comprising: a plurality of device controllers each for controlling at least one of the devices of the plurality, for the providing or receiving of data; an input-output processor connected for controlling transmission of data between the device controllers and memory; interface connecting means between the input-output processor and the device controllers including data lines and an interrupt call line, for the transfer of an interrupt call signal between device controllers and processor, there being means in the input-output processor for transmitting the call signal as interrupt request to the central processing unit for interrupting the operation thereof; first circuit means in the processor connected to obtain transfer of data between the processor and either one of the device controllers of the plurality through said interface connecting means; a plurality of flag means in the input-output processor including, a first flag means being in the set or reset state if an interrupt request signalled to the central processing unit or not, at a first operative condition of a device controller of the plurality when cooperating with the processor, and when signalling such first condition to the input-output processor, such first condition representing that the device controller and the respective device must terminate the reception or providing of data; the flag means of the plurality including second flag means being in the set or reset state if an interrupt request is to be signalled to the central processing unit or not at a second operative condition of the input-output processor, the second operative condition representing completion of data transfer between the cooperating device controller of the plurality and the memory via the input-output processor; first means in each of the device controllers including means (a) responsive to the state of device operation to provide a signal representing the first operative condition and means (b) for signaling the first operative condition to the input-output processor when cooperating therewith and through said interface connecting means; second means in the input-output processor alternatively responsive to signaling of the first condition in association with the state of the first flag means or to the existence of the second condition in association with the state of the second flag means for providing a particular order through the data lines of said interface connection to the device controller of the plurality, said particular order signaling to the device controller to request and interrupt; and an interrupt call generator in each of the device controllers responsive to an interrupt order when received from the input-output processor by operation of the second means to provide an interRupt call to said interrupt call line for transmission as interrupt request to the central processing unit, the central processing unit including third means responsive to such an interrupt request for interrupting the operation of the central processing unit then performed on data.

Claim 11

The improvement as set forth in claim 8, comprising means in the input-output processor for counting the data items transmitted between a device controller of the plurality and the input-output processor, to establish said second condition when a predeterminable number of data items have been transferred.

Claim 12

The improvement as set forth in claim 8, comprising means in the input-output processor for establishing manifestations representative of predetermined error conditions in the input-output processor-memory-device controller cooperation, the device controller being one of the plurality, the error conditions being monitored individually for the device controllers of the plurality; means in the processor for signaling the occurrence of either one of the error conditions to the device controller of the plurality through said interface connection; and means in the device controller responsive to the signaling of said occurrence to establish said first condition.

Claim 13

The improvement as set forth in claim 10, comprising means in each of the device controllers for signaling to the input-output processor when cooperating therewith, particular ones of error conditions to serve as manifestations of some of said predetermined error conditions.

Claim 14

In a general purpose digital computer, as in claim 8, the input-output processor including second circuit means for counting a predeterminable number of data items to be transferred between a device controller of the plurality and memory; the flag means of the plurality including third flag means also selectively placeable in the set and reset states for indicating data chaining; the first means in each of the device controllers connected for providing a first control signal to the processor when the respective device controller terminates acceptance or providing of data of the transfer; the first means in the processor responsive to the operation of the second circuit means and providing a second control signal to the device controller as a representation indicative of completion of counting and termination of acceptance or providing of data of the transfer by the processor; third circuit means in the processor responsive to at least one of the first and second control signals and respectively to the set state of the first and second flag defining means to provide an interrupt order to the device controller; fourth circuit means connected to the device controller and the central processing unit, and including said call generator as well as said interrupt call line for providing a program interrupt request to the central processing unit in response to the interrupt order; and fifth circuit means in the input-output processor responsive to the set state of the third flag defining means and inhibiting the rpoviding of the second control signal to the device controller so that data transfer between the device controller and the input-output processor can continue without intervention by an interrupt request.

Claim 15

The improvement set forth in claim 8, comprising means in the input-output processor for counting data items transmitted between a device controller of the plurality and the input-output processor and for establishing manifestation of the second condition when a transfer of predetermined number of data items has been counted, the second means of the input-output processor providing the particular order through the data lines of said interface connection to the device controller when a predetermined number of data items has been transferred.

Claim 16

The improvement as set forth in claim 8, including: the third means in the central processing unit responsive to the interrupt reQuest to execute a particular one of the instructions including the providing of a particular signal to the processor; the improvement further including: fourth means interconnecting the device controllers independently from the interface connection for establishing a particular order of priority rank, there being a device controller of highest and a controller of lowest priority rank, the fourth means enabling a device controller for response only if there is no device controller of higher priority ranking that has placed an interrupt call; fifth means included in the processor and in the interface connecting means for providing a function indicator signal representative of the particular signal to all said device controllers but only one device controller can respond by operation of the fourth means; sixth means included in each device controller and being responsive to said function indicator signal for providing an identifying code to said interface connection if in response to operation of said fourth means the device controller is the one of the highest priority rank among those device controllers having placed interrupt calls at the time of the providing of the function indicator signal; and seventh means in the processor responsive to the identifying code for transmitting the identifying code to the central processing unit.

Claim 17

In a general purpose digital computer having a central processing unit performing arithmetic operations on data in accordance with instructions, signal representing the instructions and the data are stored as information in a memory having a plurality of individually addressable memory locations, the computer further having a plurality of peripheral devices for input-output operations of information to be fed to memory and/or to be withdrawn therefrom, the improvement comprising: a plurality of device controllers each for controlling at least one of the devices of the plurality, for the providing or receiving of data; an input-output processor connected for controlling transmission of data between the device controllers and memory; interface connecting means between the processor and the device controllers including a first interrupt call line, for the transfer of an interrupt call signal between device controllers and processor; first means included in each device controller to provide an interrupt call signal to said first line independently from the providing of any interrupt call signal provided by any other of the device controllers to the same line, the processor receiving the call signal independent of number of call signals placed concurrently on the first line by one or more of the device controllers; second means for transmitting the call signal from the processor to the central processing unit as input-output interrupt request; third means in the central processing unit responsive to the interrupt request to execute a particular one of the instructions including the providing of a particular signal to the processor; fourth means interconnecting the device controllers independently from the interface connection for establishing a particular order of priority rank, there being a device controller of highest and a controller of lowest priority rank; fifth means included in the processor and connected to the interface connection for providing a function indicator signal to all said device controllers; sixth means included in each device controller and being responsive to said function indicator signal for providing an identifying code to said interface connection if in response to operation of said fourth means the device controller is the one of highest priority rank among those device controllers having placed interrupt calls at the time of the providing of the function indicator signal; and seventh means in the processor responsive to the identifying code for transmitting the identifying code to the central processing unit.

Claim 18

In a general purpose digital computer having a central processing unit performing arithmetic operations on data in accordance with instructions, signal representing the instructions and the data are stored as information in a memory having a plurality of individually addressable memory locations, the computer further having a plurality of peripheral devices for input-output operations of information to be fed to memory and/or to be withdrawn therefrom, the improvement comprising: a plurality of device controllers each for controlling at least one of the devices of the plurality, for the providing or receiving of data; an input-output processor connected for controlling transmission of data between the device controllers and memory; interface connecting means between the processor and the device controllers including a first interrupt call line, for the transfer of an interrupt call signal between device controllers and processor; first means included in each device controller to provide an interrupt call signal to said first line independently from the providing of any interrupt call signal provided by any other of the device controllers to the same line, the processor receiving the call signal independent of number of call signals placed concurrently on the first line by one or more of the device controllers; second means for transmitting the call signal from the processor to the central processing unit as input-output interrupt request; third means in the central processing unit responsive to the interrupt request to execute a particular one of the instructions including the providing of a particular signal to the processor; fourth means interconnecting the device controllers independently from the interface connection for establishing a particular order of priority rank, there being a device controller of highest and a controller of lowest priority rank; fifth means included in the processor and connected to the interface connection for providing a function indicator signal to all said device controllers; sixth means included in each device controller and being responsive to said function indicator signal for providing an identifying code to said interface connection if in response to operation of said fourth means the device controller is the one of highest priority rank among those device controllers having placed interrupt calls at the time of the providing of the function indicator signal; and seventh means in the processor responsive to the identifying code for transmitting the identifying code to the central processing unit.

Claim 19

In a computeR as in claim 15, and including eighth means in each device controller for signalling the cause of the interrupt signal in form of plural bit status information for the processor.

Claim 20

The improvement as set forth in claim 16, the seventh means in the input-ouput processor transmitting to the central processing unit, additionally to the device identifying information, status information which includes bits indicative of incorrect length of data transfer, data transmission error including partly error, normal and abnormal end of device operation, completion of transfer of a specified number of data items, as indication for the cause of the identified device having placed the interrupt call.

Claim 21

The improvement as set forth in claim 16, the input-output processor including flag means to indicate whether or not under current operating conditions the input-output processor is to cause a device controller to issue an interrupt under particular predetermined operating conditions when occurring, the input-output processor further including means to indicate whether these operating conditions have in fact occurred; and means in the processor to signal to the device control that the device controller issue an interrupt call signal by operation of the first means, if the flag means so indicate upon occurrance of one of these particular operating conditions.

Claim 22

In a general purpose digital computer as in claim 15, the fourth means including in each device controller a signal receiver and a priority control signal driver for providing a priority control signal to the signal receiver of the device controller of next lower priority rank, the receiver of the device controller of highest priority rank receiving an independently developed priority constrol signal, the signal receiver in each device controller receiving a signal from the driver in the device controller of next higher priority; means (a) in each device controller and connected for being responsive to particular conditions requiring connection of the respective device controller to the processor including the providing of an interrupt call, and means (b) in each device controller and connected to the receiver and to the means (a) for initiating operative connection of the device controller and processor in response to receiving a priority control signal through its receiver while inhibiting the providing of a priority control signal by its driver to the receiver in the device controller of next lower priority.

Claim 23

The improvement as set forth in claim 19, including means for connecting directly the input of a receiver in a device controller to the output of the driver thereof in the absence of power for the controller.

Claim 24

The improvement as set forth in claim 19, the device controller of lowest priority when receiving a priority control signal and not inhibiting the providing of a signal by its driver, having its driver connected to the processor to provide thereto a no-response signal.