Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
106 words
A programmable logic circuit for controlling auxiliary functions on a machine tool, the combination comprising: an interface circuit connected to a numerical control system to receive and decode auxiliary command words generated by the numerical control system and to selectively generate in response thereto STATE logic signals; an addressable storage bank containing a plurality of storage elements connected to receive and store STATE logic signals generated by the interface circuit; and a programmable controller connected to selectively address the storage elements in said addressable storage bank and programmed to read the condition of any such storage element and control the auxiliary functions on the machine tool.
Claim 2
Dependent Claim
106 words
A programmable logic circuit for controlling auxiliary functions on a machine tool, the combination comprising: an interface circuit connected to a numerical control system to receive and decode auxiliary command words generated by the numerical control system and to selectively generate in response thereto STATE logic signals; an addressable storage bank containing a plurality of storage elements connected to receive and store STATE logic signals generated by the interface circuit; and a programmable controller connected to selectively address the storage elements in said addressable storage bank and programmed to read the condition of any such storage element and control the auxiliary functions on the machine tool.
Claim 3
Dependent Claim
25 words
The circuit as recited in claim 1 in which said interface circuit includes a programmable decoder connected to receive and identify the auxiliary command words.
Claim 4
Dependent Claim
53 words
The circuit as recited in claim 2 in which said programmable decoder includes a memory which is programmed to receive auxiliary command words at a set of input terminals and in response to each, generate a digital output signal which indicates the address of a selected storage element in said addressable storage bank.
Claim 5
Dependent Claim
42 words
The circuit as recited in claim 3 in which said programmable decoder includes a decoder circuit connected to receive the digital output signals generated by said memory, and in response to each, generate a STATE logic signal to the addressed storage element.
Claim 6
Dependent Claim
48 words
The circuit as recited in claim 1 in which said programmable controller includes a memory containing a decoding program and a controller program, and in which said interface circuit includes an addressable multiplexer connected to the programmable controller and connected to receive and store the auxiliary command words.
Claim 7
Dependent Claim
54 words
The circuit as recited in claim 5 in which the decoding program operates the programmable controller to examine each bit of an auxiliary command word stored in the addressable multiplexer and to thereby identify the auxiliary command word and generate a STATE logic signal to a preselected storage element in said addressable storage bank.
Claim 8
Dependent Claim
163 words
A programmable logic circuit for coupling a programmable controller with a digital control system that generates digital command words, the combination comprising: an addressable multiplexer connected to receive and store said digital command words, said addressable multiplexer being operable in response to instructions generated by said programmable controller to read out said stored digital command words to said conroller; and An addressable storage bank connected to said programmable controller, said addressable storage bank including a plurality of storage elements which are selectively addressable by said programmable controller and which are responsive when addressed to either store a STATE logic signal generated by said programmable controller or read a stored STATE logic signal to said programmable controller; wherein said programmable controller includes a decoding program which decodes a digital command word stored in said addressable multiplexer by reading the condition of each bit thereof, and having identified said digital command word, to generate a state logic signal to one of said addressable storage elements.
Claim 9
Dependent Claim
163 words
A programmable logic circuit for coupling a programmable controller with a digital control system that generates digital command words, the combination comprising: an addressable multiplexer connected to receive and store said digital command words, said addressable multiplexer being operable in response to instructions generated by said programmable controller to read out said stored digital command words to said conroller; and An addressable storage bank connected to said programmable controller, said addressable storage bank including a plurality of storage elements which are selectively addressable by said programmable controller and which are responsive when addressed to either store a STATE logic signal generated by said programmable controller or read a stored STATE logic signal to said programmable controller; wherein said programmable controller includes a decoding program which decodes a digital command word stored in said addressable multiplexer by reading the condition of each bit thereof, and having identified said digital command word, to generate a state logic signal to one of said addressable storage elements.
Claim 10
Dependent Claim
86 words
The circuit as recited in claim 7 wherein said decoding program is stored in a controller memory with a controller program, and in which an interface control circuit is connected to receive and store in a first control flip-flop a flag signal generated by said digital control system when a digital command word is generated to said addressable multiplexer, and in which said interface control circuit is responsive to said flag signal to generate an enable signal to the addressable multiplexer and the addressable storage bank.
Claim 11
Dependent Claim
46 words
The circuit as recited in claim 8 in which a memory control circuit is connected to said controller memory, and said memory control circuit is operable to address and read out in sequence each instruction in both the decoding and controller programs stored in said memory.
Claim 12
Dependent Claim
98 words
The circuit as recited in claim 9 which includes a memory reset bus connected to said memory control circuit and connected to a recycle gate in said interface control circuit. wherein a memory reset instruction is stored at the end of said decoding program and said recycle gate is responsive to the flag signal stored in said interface control circuit and to a digital signal which results when said memory reset instruction is read from the controller memory, to generate a digital signal on said memory reset bus which operates said memory circuit to reread the decoding program.