Programmable controller expansion circuit

Claim 2

In a programmable controller having a memory which stores a set of instructions that are sequentially read out, each instruction including an address code which selects a circuit in an address bank, and each instruction including an operation code which selects a function to be performed by a central logic unit in the programmable controller, the improvement therein comprising an expander circuit which includes: a plurality of pairs of address banks; a summing circuit connected to each of said pairs of address banks; an electronic switch circuit connected to said summing circuit to selectively enable one of said pairs of address banks in response to an instruction read from the controller memory; and a gate circuit connected to said summing circuit to selectively activate one of said eNabled address banks in response to an instruction read from the controller memory which includes both a non-addressable operation code and an address code; wherein a circuit in said enabled, activated address bank is paged by said address code.

Claim 3

The expander circuit as recited in claim 1 wherein said electronic switch circuit includes a plurality of flip-flops responsive to selected instructions read from said controller memory to selectively enable one of said address bank pairs by generating an enabling signal to said summing circuit.

Claim 4

The expander circuit as recited in claim 2 wherein said gate circuit includes a logic gate responsive to selected instructions read from said controller memory to activate one of said address banks in each pair by generating an actuate signal to said summing circuit.

Claim 5

The expander circuit as recited in claim 3 wherein said summing circuit includes a plurality of summing logic gates, each summing logic gate having an output terminal connected to an address bank, one input terminal connected to the electronic switch circuit, and one input terminal connected to said gate circuit, wherein a circuit in an address bank is activated and enabled when its attached summing logic gate received an enabling signal from said electronic switch circuit and an activate signal from said gate circuit.

Claim 6

In a programmable controller having a memory which stores a set of instructions that are sequentially read out, each instruction including an address code which selects an input or output device connected to a first address bank in the programmable controller, and each instruction including an operation code which selects a function to be performed by a central logic unit in the programmable controller, the improvement therein comprising an expander circuit which includes: gate means having a first input terminal connected sense the operation code in each instruction read from said memory, a second input terminal connected to sense the address code in each instruction read from said memory, and an output terminal connected to said central logic unit and said first address bank; and a second address bank connected to said gate means and being responsive to the address code in each instruction read from said memory, wherein said operation codes are either addressable or non-addressable and said gate means is responsive to each instruction which includes both a non-addressable operation code and an address code to generate a preselected addressable operation signal to said central logic unit, to deactivate said first address bank, and to activate said second address bank.

Claim 7

In a programmable controller having a memory which stores a set of instructions that are sequentially read out, each instruction including an address code which selects an input or output device connected to a first address bank in the programmable controller, and each instruction including an operation code which selects a function to be performed by a central logic unit in the programmable controller, the improvement therein comprising an expander circuit which includes: gate means having a first input terminal connected sense the operation code in each instruction read from said memory, a second input terminal connected to sense the address code in each instruction read from said memory, and an output terminal connected to said central logic unit and said first address bank; and a second address bank connected to said gate means and being responsive to the address code in each instruction read from said memory, wherein said operation codes are either addressable or non-addressable and said gate means is responsive to each instruction which includes both a non-addressable operation code and an address code to generate a preselected addressable operation signal to said central logic unit, to deactivate said first address bank, and to activate said second address bank.

Claim 8

The circuit as recited in claim 5 in which the programmable controller includes an address decoder connected to receive the address code in each instruction read from the memory and an operation decoder connected to receive the operation code in each instruction read from the memory, wherein said gate means includes: a first logic gate having a first input terminal connected to said operation decoder, a second input terminal connected to said address decoder, and an output terminal connected to said central logic unit; an EXP bus connected to the output terminal of said first logic gate and to one of said address banks; a NOT gate having an input terminal connected to said EXP bus and an output terminal; and an EXP bus connected to the output terminal of said NOT gate and to the other of said address banks.