Technique for detecting memory failures and to provide for automatically for reconfiguration of the memory modules of a memory system

Claim 2

A data processing system comprising: a plurality of independently addressable memory modules; a plurality of module positioning means, a first one of said positioning means being coupled to receive a predetermined set of input address signals, each of the remaining ones of said positioning means being coupled to receive input signals from a preceding positioning means, said each positioning means including means to modify said input signals to generate output address signals corresponding to a different logical address to be applied to a succeeding one of said positioning means and to the associated one of said modules; error detecting means coupled to each of said memory modules for sensing a minimum standard of reliability for said memory modules, said error detecting means including checking means to generate a check error signal each time said detecting means senses that an accessed module has failed to meet said minimum standard indicating that said accessed module is faulty; storage means coupled to said error detecting means, said storage means being conditioned by said checking means to store status signals indicating the occurrence of check error signal sensed during the accessing of any of said plurality of modules; logic means coupled to said storage means, said logic means being operative in response to a command signal to apply inhibit control signals to the positioning means associated with modules having a check condition, the last mentioned positioning means being conditioned by said control signals to inhibit modifying said input signals so as to alter the generation of certain assigned logical addresses enabling all faulty memory modules to be disconnected and the reconfiguration of the remaining memory modules to provide a continuous addressable address space.

Claim 3

The system of claim 1 further including a plurality of module selection means, one individually coupled to each of said plurality of positioning means and to an associated one of said modules, each of said module selection means including means for receiving said output signals from the associated positioning means and a plurality of address signals coded to designate logical addresses of each of said plurality of memory modules selected for access and said logic means being individually coupled to each of said plurality of selection means, said logic means being operative to apply said control signals to the module selection means of each faulty module to inhibit access of each said module in response to said plurality of address signals.

Claim 4

The system of claim 1 wherein each of said positioning means includes input means for receiving said input address signals and output means for receiving said address signals generated by said positioning means corresponding to said logical address; said positioning means of any one of said modules detected to be faulty being conditioned by said conTrol signals to pass said input address signals to said output means unmodified and said address positioning means of each of the remaining modules being conditioned by said logic means to perform an arithmetic operation upon said input address signals and apply the results of said operation corresponding to said assigned logical address to said output means for application to the input means of a succeeding one of said plurality of positioning means.

Claim 5

The system of claim 1 further including: a central processing unit, said central processing unit including means coupled to said error detecting means, said means being operative in response to said check error signal to generate said command signal initiating the reconfiguration of said remaining ones of plurality of memory modules.

Claim 6

The system of claim 2 wherein each of said positioning means includes an adder circuit, said adder circuit of each of said positioning means of said remaining ones of said memory modules being conditioned by said logic means to increment by one said input address signals and said adder circuit of said any one of said faulty modules being conditioned by said control signals to inhibit said adder circuit from incrementing by one said input address signals thereby enabling a succeeding one of said positioning means to assign the next sequential logical address to the memory module associated therewith.

Claim 7

The system of claim 1 wherein each of said plurality of memory modules includes a plurality of addressable storage locations and wherein said error detecting means includes: error sensing means coupled to each of said plurality of addressable memory modules, said error sensing means includes module checking means operatively coupled to each of said plurality of memory modules, said means being operative to perform a checking operation upon the contents of a memory storage location of an accessed memory module and generate said check error signal when the contents of said accessed module are in error; and wherein said storage means including a plurality of bistable storage means, each of said plurality of bistable storage means being operative to store a signal indicating the operational status of a different one of said memory modules in response to check error signals generated by said error sensing means, said plurality of bistable storage means being coupled to apply signals indicating said status of said plurality of memory modules to said logic means; and, said logic means being responsive to said command signal and to said signals to inhibit each of said positioning means coupled to one of said bistable storage means which stores said signal that the module associated therewith is faulty, from modifying said input address signals.

Claim 8

The system of claim 6 wherein said module checking means of said error sensing means includes parity generation circuit means for signalling the occurrence of a parity error in said contents and wherein each of said plurality of bistable storage means are conditioned by said sensing means to be switched from a first state to a second state the first time the contents of a storage location of an accessed memory module is sensed as having a parity error.

Claim 9

The system of claim 6 wherein said logic means includes a plurality of bistable storage elements, one individually associated with each of said plurality of bistable storage means of said storage means, each of said plurality of bistable storage elements of said logic means being coupled to receive a signal from the associated one of said plurality of said bistable storage means and each of said plurality of bistable storage elements being coupled to the positioning means of one of said plurality of memory modules, each of said bistable storage elements being operative in response to said command signal to switch from a first state to a second state in accordance with the state of the associated bistable storage means.

Claim 10

The system of claim 7 wherein each of said pluralIty of bistable storage means of said storage means include means for receiving a clear signal, each of said plurality of storage devices switched to said second state being conditioned by said clear signal to switch from said second state to said first state thereby enabling said error detecting means to condition said storage means for storing signals indicating said sensing of subsequent check error signals.

Claim 11

The system of claim 7 further including a plurality of display indicator circuit means, each of said plurality of display indicator circuits being coupled to a different one of said plurality of bistable storage means of said error status means and each of said plurality of indicator circuits being conditioned by signals from said different one of said plurality of bistable storage means to display an indication of the status of the memory module associated therewith.

Claim 12

The system of claim 8 wherein each of said bistable storage elements of said logic means includes means for receiving a different one of a plurality of control signals, each of said bistable storage elements being operative in response to said control signal to switch from said first to said second state inhibiting corresponding ones of said address positioning means from altering said input signals and thereby enabling any one of said memory modules to be isolated for test purposes.

Claim 13

The system of claim 8 further including a central processing unit coupled to said error sensing means and to said bistable storage elements of said storage means, said central processing unit including means operative in response to said checking error signal to enter a predetermined error recovery program routine which results in the generation of said command signal so as to condition said plurality of address positioning means to cause the reconfiguration of said plurality of memory modules to form said continuous address space.

Claim 14

The system of claim 8 wherein each of said plurality of storage elements and each of said bistable storage means include means for receiving a clear control signal and wherein said system further includes a central processing unit coupled to said error sensing means and to said logic means, said central processing unit including means operative in response to said checking error signal to enter a predetermined error recovery program routine resulting in the conditioning of said central processing unit to generate said clear signal indicating that reconfiguration is not required.

Claim 15

The system of claim 11 further including a plurality of manually controlled switching means, each of said plurality of manually controlled switching means being coupled to a different one of said bistable storage elements and each of said switching means being connected to apply said differnt one of said control signals to said different one of said bistable storage elements.

Claim 16

The system of claim 11 further including manually controlled switching means coupled to said bistable storage elements of said storage means, said switching means being operative when switched to generate said command signal so as to condition said plurality of positioning means to cause a reconfiguration of said plurality of memory modules to form said continuous address space.

Claim 17

The system of claim 1 further including a plurality of module selection means, each of said module selection means being coupled to a different one of said positioning means and to a different one of said memory modules, and each of said plurality of module selection means including means for receiving a plurality of address signals coded to designate logical addresses of each of said plurality of memory modules selected for access and wherein each of said address positioning means includes: adder circuit means including means for receiving said input address signals; and, comparison means coupled to said adder circuit means and including: first input means for receiving a plurality of input signals representative of the maximum number of memory modules to be operative within the system, second input means for receiving said input address signals, and output circuit means for generating a control signal indicating when the maximum allowable address is exceeded, each of said adder circuit means being inhibited by said control signal from the associated comparison means from modifying said input address signals, the adder circuit means of a last one of said plurality of address positioning means being operative to generate output signals representative of the number of memory modules operating within the system, and, each of said module selection means being inhibited by said control signal from said comparison means from allowing access to said memory module when designated for access by said plurality of input address signals.

Claim 18

The system of claim 16 further including jumper circuit means connected to generate said input signals representative of said maximum number of memory modules operating within said system.

Claim 19

The system of claim 17 wherein said jumper circuit means are connected to generate input signals coded to specify maximum number less than said plurality of memory modules thereby providing a predetermined number of spare modules.

Claim 20

The system of claim 16 further including a central processing unit coupled to said last one of said plurality of positioning means, said central processing unit including: comparison means having first input means for receiving address signals designating one of said plurality of modules specified for access, second input means for receiving said output signals, and output circuit means for generating a signal representing a non-existent memory error condition when said comparison means senses a true comparison between said signals applied to said first and second input means.

Claim 21

The system of claim 16 further including input jumper circuit means coupled to an adder circuit means of a first one of said plurality of positioning means, said input jumper means connected to generate input signals coded to represent one less than said lowest numerical assignable logical address.

Claim 22

The system of claim 20 wherein said lowest numerical address corresponds to an all zero code and wherein said highest numerical logical address corresponds to the number of operative memory modules.

Claim 23

A data processing system comprising: a central processing means including means for generating a command signal; and, a memory system coupled to said central processing means, said memory system including a plurality of memory interfaces, each of said interfaces including: a plurality of independently addressable memory modules, each connected in common to share a common input/output bus; a plurality of positioning means, one individually associated with each of said plurality of memory modules and each one including: input means for receiving input address signals, adder means coupled to receive said input address signals from said input means and operative to modify said input address signals to generate signals representative of an assigned logical address used to select for access the associated one of said memory modules, and output means coupled to receive said signals from said adder means; a first one of said plurality of address positioning means being connected to receive initial predetermined address signals which are used to define the logical address of the module assigned the lowest numerical value, each of the remaining ones of said plurality of address positioning means being connected in tandem so that an adder circuit of each of said remaining ones of said positioning means is connected to receive input address signals from a preceding one of said remaining ones of said address positioning means and said adder circuit output means is connected to apply said logical address to a succeeding one of said remaining ones of said address positioning means; erRor detecting means being operatively coupled to each of said memory modules of said interface, said error detecting means being operative to generate a check error signal each time said error detecting means senses that a memory module selected for access has performed a cycle of operation incorrectly indicating that the module accessed is faulty; storage means coupled to said error detecting means, for storing indications of those modules selected for access indicated as being faulty; and, logic means coupled to said storage means and to each of said address positioning means, said logic means being operative in response to a command signal to generate signals indicating those memory modules selected for access which have been indicated as being faulty, the adder means of each faulty module being inhibited by said signals from altering the input address signals thereby changing the assignment of logical addresses so as to enable all faulty memory modules to be disconnected and the reconfiguration of the remaining ones of said plurality of memory modules to provide a continuous new address space.

Claim 24

A data processing system comprising: a central processing means including means for generating a command signal; and, a memory system coupled to said central processing means, said memory system including a plurality of memory interfaces, each of said interfaces including: a plurality of independently addressable memory modules, each connected in common to share a common input/output bus; a plurality of positioning means, one individually associated with each of said plurality of memory modules and each one including: input means for receiving input address signals, adder means coupled to receive said input address signals from said input means and operative to modify said input address signals to generate signals representative of an assigned logical address used to select for access the associated one of said memory modules, and output means coupled to receive said signals from said adder means; a first one of said plurality of address positioning means being connected to receive initial predetermined address signals which are used to define the logical address of the module assigned the lowest numerical value, each of the remaining ones of said plurality of address positioning means being connected in tandem so that an adder circuit of each of said remaining ones of said positioning means is connected to receive input address signals from a preceding one of said remaining ones of said address positioning means and said adder circuit output means is connected to apply said logical address to a succeeding one of said remaining ones of said address positioning means; erRor detecting means being operatively coupled to each of said memory modules of said interface, said error detecting means being operative to generate a check error signal each time said error detecting means senses that a memory module selected for access has performed a cycle of operation incorrectly indicating that the module accessed is faulty; storage means coupled to said error detecting means, for storing indications of those modules selected for access indicated as being faulty; and, logic means coupled to said storage means and to each of said address positioning means, said logic means being operative in response to a command signal to generate signals indicating those memory modules selected for access which have been indicated as being faulty, the adder means of each faulty module being inhibited by said signals from altering the input address signals thereby changing the assignment of logical addresses so as to enable all faulty memory modules to be disconnected and the reconfiguration of the remaining ones of said plurality of memory modules to provide a continuous new address space.

Claim 25

The system of claim 22 including means for coupling said central processing means to a last one of said plurality of address positioning means included each of said plurality of memory interfaces for receiving signals representative of an assigned logical address having the highest numerical value and said last one of said plurality of address positioning means of each memory interface being conditioned by the address positioning means of said faulty modules to decrease said logical address having said highest numerical value by the number of faulty modules thereby indicating to said central processing means the remaining number of modules operating in each of said plurality of memory interfaces.

Claim 26

A memory system for use in a data processing system comprising: a plurality of independently addressable memory modules; a corresponding number of module select means, each of said module select means being coupled to a different one of said plurality of memory modules, each of said module select means including input means for receiving a plurality of address selection signals designating which of said plurality of memory modules has been addressed for access, and output means for generating signals for accessing said module; error detection means operatively coupled to each of said plurality of memory modules, said error detection means including means for sensing a minimum standard of reliability for information accessed from said memory modules; storage means coupled to said means for sensing for generating signals indicating when any one of said memory modules has failed to meet said minimum standard signalling that the module has failed; reconfiguration logic means coupled to said storage means and to each of said memory module select means, said reconfiguration logic means including a plurality of address positioning means, one individually associated with each of said plurality of memory modules, a first one of said positioning means being coupled to receive a predetermined set of address signals, the remaining ones of said positioning means being coupled in tandem so that each positioning means receives input address from a preceding positioning means and said each positioning means being operative to modify said address signals and apply said modified address signals to a succeeding positioning means and to the select means of the associated module; and, purge logic means coupled to each of said plurality of address positioning means and to each of said number of module select means, said purge logic means coupled to said storage means, said purge logic means being operative in response to a command signal to apply signals to each of said plurality of address positioning means and to each of said selection means of any one of said memory modules specified by said signals from said storage means as having failed, said control sIgnals conditioning said address positioning means from modifying the input address signals and conditioning the module selection means associated therewith from generating signals for accessing said module in response to said plurality of address selection signals.

Claim 27

A memory system for use in a data processing system comprising: a plurality of independently addressable memory modules; a corresponding number of module select means, each of said module select means being coupled to a different one of said plurality of memory modules, each of said module select means including input means for receiving a plurality of address selection signals designating which of said plurality of memory modules has been addressed for access, and output means for generating signals for accessing said module; error detection means operatively coupled to each of said plurality of memory modules, said error detection means including means for sensing a minimum standard of reliability for information accessed from said memory modules; storage means coupled to said means for sensing for generating signals indicating when any one of said memory modules has failed to meet said minimum standard signalling that the module has failed; reconfiguration logic means coupled to said storage means and to each of said memory module select means, said reconfiguration logic means including a plurality of address positioning means, one individually associated with each of said plurality of memory modules, a first one of said positioning means being coupled to receive a predetermined set of address signals, the remaining ones of said positioning means being coupled in tandem so that each positioning means receives input address from a preceding positioning means and said each positioning means being operative to modify said address signals and apply said modified address signals to a succeeding positioning means and to the select means of the associated module; and, purge logic means coupled to each of said plurality of address positioning means and to each of said number of module select means, said purge logic means coupled to said storage means, said purge logic means being operative in response to a command signal to apply signals to each of said plurality of address positioning means and to each of said selection means of any one of said memory modules specified by said signals from said storage means as having failed, said control sIgnals conditioning said address positioning means from modifying the input address signals and conditioning the module selection means associated therewith from generating signals for accessing said module in response to said plurality of address selection signals.

Claim 28

In a data storage system including a plurality of independently addressable memory modules and a plurality of module select circuits, each being operative to select the associated memory module for access in response to a set of module address signals, a reconfiguration control system comprising: a plurality of module positioning means, one individually associated with each of said plurality of module select circuits, a first one of said positioning means being connected to receive predetermined input address signals, the remaining ones of said positioning means being coupled in tandem so that each positioning means receives input address signals from a positioning means of a preceding module and applies modified address signals corresponding to a logical address as input to a positioning means of a succeeding module and to said one select circuit; checking means connected to be accessible to each of said memory modules, said checking means being operative to detect a check condition by performing checking operation upon the information bits accessed from a module selected in response to said set of module address signals; a plurality of storage means coupled to said checking means, one individually associated with each memory module and arranged to store a signal indicating the occurrence of a check condition within said associated module when detected by said checking means; and, logic means coupled to said plurality of storage means and said plurality of module positioning means, said logic means including means for receiving a control signal, said logic means being operative in response to said control signal to apply signals to the select circuits and positioning means associated with each of said plurality of storage means indicating said check condition, said last mentioned select circuits being conditioned by said signals to inhibit access to the associated modules and said last mentioned positioning means being conditioned by said signals to inhibit modifying said input signals thereby altering the assignment of logical addresses providing a reconfiguration of the remaining modules thereby forming a new continuous address space.

Claim 29

In a data storage system including a plurality of independently addressable memory modules and a plurality of module select circuits, each being operative to select the associated memory module for access in response to a set of module address signals, a reconfiguration control system comprising: a plurality of module positioning means, one individually associated with each of said plurality of module select circuits, a first one of said positioning means being connected to receive predetermined input address signals, the remaining ones of said positioning means being coupled in tandem so that each positioning means receives input address signals from a positioning means of a preceding module and applies modified address signals corresponding to a logical address as input to a positioning means of a succeeding module and to said one select circuit; checking means connected to be accessible to each of said memory modules, said checking means being operative to detect a check condition by performing checking operation upon the information bits accessed from a module selected in response to said set of module address signals; a plurality of storage means coupled to said checking means, one individually associated with each memory module and arranged to store a signal indicating the occurrence of a check condition within said associated module when detected by said checking means; and, logic means coupled to said plurality of storage means and said plurality of module positioning means, said logic means including means for receiving a control signal, said logic means being operative in response to said control signal to apply signals to the select circuits and positioning means associated with each of said plurality of storage means indicating said check condition, said last mentioned select circuits being conditioned by said signals to inhibit access to the associated modules and said last mentioned positioning means being conditioned by said signals to inhibit modifying said input signals thereby altering the assignment of logical addresses providing a reconfiguration of the remaining modules thereby forming a new continuous address space.