Improved shift register having (n/2 - 1) stages for digitally synthesizing an n-phase sinusoidal waveform

Claim 2

A circuit for digitally synthesizing a stepped approximation of a sinusoidal waveform having a fundamental frequency F0 and having N phases of equal duration per cycle of the waveform, where N is an even integer greater than or equal to six, said circuit comprising: a shift register having plural serially connected stages; means for coupling a shifting signal having a frequency Nf0 to each of said stages; means for coupling a digital signal having a repetition frequency f0 into the signal input of a first one of said stages; a summing terminal; and no more than ((N/2-1)) output resistors, each of said resistors connecting from said summing terminal to the signal output of a different one of said stages.

Claim 3

A shift register circuit comprising: a plurality of shift register stages connected in a serial string; means for coupling a shifting signal to the shifting signal input of each of said stages; means for coupling a digital waveform into the signal input of the first stage in said serial string of stages; a summing terminal; and no more that ((N/2-1)) resistors, each of which commects between said summing terminal and the signal output of a different one of said stages and the values of which relate to one another in accordance with the formula Ri K/(cos(2 pi i/N + pi /N) - cos(2 pi (i-1)/N+ pi /N)), where N is an even integer greater than or equal to six, i is an integral index variable corresponding to the number of the stage to which the resistor having that subscript number is connected, i ranging from 1 to ((N/2-1)) (beginning at the first stage of said string of stages), and K is a constant of proportionality.

Claim 4

A shift register circuit comprising: a plurality of shift register stages connected in a serial string; means for coupling a shifting signal to the shifting signal input of each of said stages; means for coupling a digital waveform into the signal input of the first stage in said serial string of stages; a summing terminal; and no more that ((N/2-1)) resistors, each of which commects between said summing terminal and the signal output of a different one of said stages and the values of which relate to one another in accordance with the formula Ri K/(cos(2 pi i/N + pi /N) - cos(2 pi (i-1)/N+ pi /N)), where N is an even integer greater than or equal to six, i is an integral index variable corresponding to the number of the stage to which the resistor having that subscript number is connected, i ranging from 1 to ((N/2-1)) (beginning at the first stage of said string of stages), and K is a constant of proportionality.

Claim 5

A tapped delay circuit for digitally synthesizing a sinusoidal waveform, comprising: a serial shift register for providing at tapped signal outputs thereof plural differently delayed components of a digital waveform; a common summing terminal; resistive means for coupling said differently delayed components from said tapped outputs to said common summing terminal, including plural resistors having values in accordance with the formula Ri K/(cos(2 pi i/N + pi /N) - cos(2 pi (i-1)/N + pi /N)), where i is an integral index variable, K is a constant of proportionality, and N is an even integer of greater than or equal to six and of a magnitude selected in accordance with the degree of harmonic distortion in the resulting synthesized waveform.

Claim 6

A tapped delay circuit for digitally synthesizing a sinusoidal waveform, comprising: a serial shift register for providing at tapped signal outputs thereof plural differently delayed components of a digital waveform; a common summing terminal; resistive means for coupling said differently delayed components from said tapped outputs to said common summing terminal, including plural resistors having values in accordance with the formula Ri K/(cos(2 pi i/N + pi /N) - cos(2 pi (i-1)/N + pi /N)), where i is an integral index variable, K is a constant of proportionality, and N is an even integer of greater than or equal to six and of a magnitude selected in accordance with the degree of harmonic distortion in the resulting synthesized waveform.

Claim 7

A circuit in accordance with claim 3 wherein said shift register comprises ((N/2-1)) stages; and said resistive means includes ((N/2-1)) output resistors.

Claim 8

A circuit in accordance with claim 3 wherein said shift register comprises no more than ((N/2-2)) stages; and said resistive means includes no more than ((N/2-1)) output resistors.

Claim 9

A circuit in accordance with claim 4 wherein said shift register comprises ((N/2-2)) stages; and said resistive means includes no more than ((N/2-2)) output resistors.