Adaptive transversal equalizer using a time-multiplexed second-order digital filter

Claim 2

A digital filter for producing an equalized output from a distorted input signal comprising first and second delay storage units in tandem, a first and second pair of adjustable gain devices respectively connected to each of said delay storage units, an accumulating adder for combining signals operated on by one of each pair of said gain devices, means for connecting the other of each pair of said gain devices to control said one of each pair of said gain devices, an error detection circuit connected to said adder, means for applying error signals from said error detection circuit to the others of each of said pairs of gain devices for correlation with the delayed input signal thereat, first means for selectively looping the output of each said delay unit to its own input, and second means for selectively looping the output of said second delay unit to the input of said first delay unit.

Claim 3

The digital filter defined in claim 1 in which each of said delay storage units is a multistage shift register having at least as many stages as there are bits in each digitally encoded sample of said input signal.

Claim 4

The digital filter defined in claim 1 further comprising a recirculating storage register for tap-gain control signals to be applied to each of said first pair of gain devices, and means of scaling said error signals used in determining the magnitude of incrementation of said storage register.

Claim 5

The digital filter defined in claim 1 in which a switchable recirculation loop is connected between output and input of said adder to permit augmentation of prior stored sums of tap-gain controlled signals with additional sums of tap-gain controlled signals.

Claim 6

The digital filter defined in claim 1 in combination with control means for predetermining which of said first and second looping means is operative at any given time.

Claim 7

A second-order digital filter including two delay storage units in tandem, first and second pairs of gain-control devices connected to said delay units and input and output adder circuits to each of which are normally connected one each of said first and second pairs of gain devices: further comprising a first selectable recirculation loop around said output adder, second and third selectable recirculation loops around each of said delay storage units, a fourth selectable recirculation loop around both of said delay storage units in tandem, an error detector connected to said output adder for determining from a comparison with a quantized level the direction of the output signal error, means for applying signals from said error detector to one gain device of each of said first and second pairs of gain devices for correlation with input signal samples stored in said delay units, storage registers for gain coefficients controlling the other of each of said first and second pairs of gain devices, and means for transferring the outputs of the ones of each of said first and second pairs of gain devices between said input adder circuit and said storage registers.

Claim 8

A second-order digital filter including two delay storage units in tandem, first and second pairs of gain-control devices connected to said delay units and input and output adder circuits to each of which are normally connected one each of said first and second pairs of gain devices: further comprising a first selectable recirculation loop around said output adder, second and third selectable recirculation loops around each of said delay storage units, a fourth selectable recirculation loop around both of said delay storage units in tandem, an error detector connected to said output adder for determining from a comparison with a quantized level the direction of the output signal error, means for applying signals from said error detector to one gain device of each of said first and second pairs of gain devices for correlation with input signal samples stored in said delay units, storage registers for gain coefficients controlling the other of each of said first and second pairs of gain devices, and means for transferring the outputs of the ones of each of said first and second pairs of gain devices between said input adder circuit and said storage registers.

Claim 9

A digital filter section adapted to interchangeable connection as either a recursive filter or a nonrecursive adaptive equalizer comprising not fewer than first and second delay storage units in tandem, first and second pairs of adjustable gain devices connected to the outputs of each of said delay storage units, first and second adders respectively connectable to the input of said first delay stOrage unit only and to the outputs of all of said delay storage units, means for connecting one of each of said pairs of gain devices to said second adders, means for selectively connecting the other of each of said pairs of gain devices in the alternative to said first adder whereby said filter section is in recursive form or to the one of each of said pairs of gain devices as gain control means whereby said filter section is in nonrecursive equalizer form, an error detection circuit connected to said second adder, means for selectively applying error signals from said error detection circuit to the other of each of said pairs of gain devices for correlation with the delayed input signal thereat, first means for selectively looping the output of each delay storage unit to its own input during operation as an equalizer, second means for selectively looping the output of the last said delay storage unit to the input of said first delay storage unit during operation as an equalizer, and control means for determining the selective operation of said digital filter section in both recursive and nonrecursive forms.

Claim 10

A digital filter section adapted to interchangeable connection as either a recursive filter or a nonrecursive adaptive equalizer comprising not fewer than first and second delay storage units in tandem, first and second pairs of adjustable gain devices connected to the outputs of each of said delay storage units, first and second adders respectively connectable to the input of said first delay stOrage unit only and to the outputs of all of said delay storage units, means for connecting one of each of said pairs of gain devices to said second adders, means for selectively connecting the other of each of said pairs of gain devices in the alternative to said first adder whereby said filter section is in recursive form or to the one of each of said pairs of gain devices as gain control means whereby said filter section is in nonrecursive equalizer form, an error detection circuit connected to said second adder, means for selectively applying error signals from said error detection circuit to the other of each of said pairs of gain devices for correlation with the delayed input signal thereat, first means for selectively looping the output of each delay storage unit to its own input during operation as an equalizer, second means for selectively looping the output of the last said delay storage unit to the input of said first delay storage unit during operation as an equalizer, and control means for determining the selective operation of said digital filter section in both recursive and nonrecursive forms.