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US3795900A Expired / Lapsed US ⏱️ 0.0 years remaining

Multifunction audio digitizer

Assignee: National Aeronautics and Space Administration
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Filing: 1971-11-09
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Granted: 1974-03-05
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Expires: 1991-11-09
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Abstract

Abstract An illustrative embodiment of the present invention includes apparatus which simultaneously produces both direct delta modulation and pulse code modulation. An input signal, after amplification, is supplied to a window comparator which supplies a polarity control signal to gate the output of a clock to the appropriate input of a binary up-down counter depending on whether the slope of the input signal is positive or negative. The control signals provide direct delta modulation while the updown counter output provides pulse code modulation.

Inventors

  • 👤 L Monford

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-23 16:40
CPC Classifications
H; H03; H03M; H03M1/00; H03M1/12; H03M1/48; H03M3/00; H03M3/02

Claims Analysis

Total Claims: 2
Claim 1
Independent Claim 373 words
Apparatus for encoding data waveforms for modulating data transmission apparatus comprising: a. transducer means for deriving an analog voltage signal representative of the input signal; b. controlled analog amplifier means for amplifying said representative analog voltage signal; c. analog adder means for algebraically adding said representative analog voltage signal to a second analog voltage signal which is derived by feedback means, thereby forming a composite signal potentiometer for manually controlling the input bias of said adder means; d. window comparator means, having a comparison window whose width is preset to the analog equivalent of one binary step, for detecting the magnitude of said composite signal and for generating a ''''count-up'''' signal at a first output terminal of said comparator means when said composite signal exceeds a preset negative threshold, and a ''''count-down'''' signal at a second output terminal of said comparator means when said composite signal exceeds a preset positive threshold, thereby tending to maintain said composite signal at zero; e. timing pulse generator means for generating timing pulses for timing the system; f. a pair of control gates for receiving, as first inputs, the respective ''''count-up'''' or ''''count-down'''' signals from said comparator means; for receiving, as second inputs, said timing pulses; and for producing delta modulation output signals only when said first input is present and is in coincidence with said timing pulse; output means for extracting said delta modulation signals; g. digital up-down counter means for receiving and counting said delta modulation output signals in either a count-up or countdown direction, thereby producing pulse-code-modulation signals at the output of said counter means which equal the analog input signal when both of said control gates have no output output means for extracting said pulse code modulation signals; a peak modulation monitor for monitoring the carry line of the said counter means; h. means responsive to said control gates for supplying said delta output modulation signals to only one at a time of said counter means inputs, thereby producing a delTa modulation signal with a count-up, count-down, or no-count format; and i. digital-to-analog converter means for monitoring the output of said counter means and for generating an analog feedback signal for application as said second analog voltage signal to said analog adder means.
Claim 2
Dependent Claim 373 words
Apparatus for encoding data waveforms for modulating data transmission apparatus comprising: a. transducer means for deriving an analog voltage signal representative of the input signal; b. controlled analog amplifier means for amplifying said representative analog voltage signal; c. analog adder means for algebraically adding said representative analog voltage signal to a second analog voltage signal which is derived by feedback means, thereby forming a composite signal potentiometer for manually controlling the input bias of said adder means; d. window comparator means, having a comparison window whose width is preset to the analog equivalent of one binary step, for detecting the magnitude of said composite signal and for generating a ''''count-up'''' signal at a first output terminal of said comparator means when said composite signal exceeds a preset negative threshold, and a ''''count-down'''' signal at a second output terminal of said comparator means when said composite signal exceeds a preset positive threshold, thereby tending to maintain said composite signal at zero; e. timing pulse generator means for generating timing pulses for timing the system; f. a pair of control gates for receiving, as first inputs, the respective ''''count-up'''' or ''''count-down'''' signals from said comparator means; for receiving, as second inputs, said timing pulses; and for producing delta modulation output signals only when said first input is present and is in coincidence with said timing pulse; output means for extracting said delta modulation signals; g. digital up-down counter means for receiving and counting said delta modulation output signals in either a count-up or countdown direction, thereby producing pulse-code-modulation signals at the output of said counter means which equal the analog input signal when both of said control gates have no output output means for extracting said pulse code modulation signals; a peak modulation monitor for monitoring the carry line of the said counter means; h. means responsive to said control gates for supplying said delta output modulation signals to only one at a time of said counter means inputs, thereby producing a delTa modulation signal with a count-up, count-down, or no-count format; and i. digital-to-analog converter means for monitoring the output of said counter means and for generating an analog feedback signal for application as said second analog voltage signal to said analog adder means.

References Cited (Backward Citations)

US3091664A Cited
US3339142A Cited
GB1028954A Cited
US3467876A Cited
US3544895A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1977-03-04 1977-09-03 1978-03-05 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1981-03-04 1981-09-03 1982-03-05 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1985-03-04 1985-09-03 1986-03-05 $7700.00 Window Closed / Lapsed

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