Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
177 words
A restOration system for restoring omitted dots of dot-typed patterns indicated by an alternate arrangement of black dots and white dots in bilateral scanning lines and vertical scanning lines comprising: memory means comprising a number of bistable memory elements for simultaneously storing one dot of each of the dot typed patterns and at least a right dot, a left dot, an upper dot and a lower dot of said one dot, means connected to said memory means for shifting said dots in said memory means in synchronism with the clock timing of the dot-typed patterns. detection means coupled to said memory means for generating a detected output when the right dot, the left dot, the upper dot and the lower dot assume predetermined states determined in accordance with the characteristics of the dot-typed patterns, and means coupled to said memory means and said detection means for obtaining in the same clock timing as the dot-typed patterns a logical sum of said one dot and said detected output of said detection means so as to provide restored patterns.
Claim 2
Dependent Claim
177 words
A restOration system for restoring omitted dots of dot-typed patterns indicated by an alternate arrangement of black dots and white dots in bilateral scanning lines and vertical scanning lines comprising: memory means comprising a number of bistable memory elements for simultaneously storing one dot of each of the dot typed patterns and at least a right dot, a left dot, an upper dot and a lower dot of said one dot, means connected to said memory means for shifting said dots in said memory means in synchronism with the clock timing of the dot-typed patterns. detection means coupled to said memory means for generating a detected output when the right dot, the left dot, the upper dot and the lower dot assume predetermined states determined in accordance with the characteristics of the dot-typed patterns, and means coupled to said memory means and said detection means for obtaining in the same clock timing as the dot-typed patterns a logical sum of said one dot and said detected output of said detection means so as to provide restored patterns.
Claim 3
Dependent Claim
183 words
A restoration system for restoring omitted dots of dot typed patterns indicated by an alternate arrangement of black dots and white dots in bilateral scanning lines and vertical scanning lines comprising: shift register means comprising a number of bistable memory elements for simultaneously storing one dot of each of the dot typed patterns and at least a right dot, a left dot, an upper dot and a lower dot of said one dot, means connected to said shift register means for shifting said dots in said shift register means in synchronism with the clock timing of the dot-typed patterns, detection means coupled to said shift register means for generating a detected output when the right dot, the left dot, the upper dot and the lower dot assume predetermined states determined in accordance with the characteristics of the dot-typed patterns, and means coupled to said shift register means and said detection means for obtaining in the same clock timing as the dot-typed patterns a logical sum of said one dot and said detected output of said detection means so as to provide restored patterns.
Claim 4
Dependent Claim
183 words
A restoration system for restoring omitted dots of dot typed patterns indicated by an alternate arrangement of black dots and white dots in bilateral scanning lines and vertical scanning lines comprising: shift register means comprising a number of bistable memory elements for simultaneously storing one dot of each of the dot typed patterns and at least a right dot, a left dot, an upper dot and a lower dot of said one dot, means connected to said shift register means for shifting said dots in said shift register means in synchronism with the clock timing of the dot-typed patterns, detection means coupled to said shift register means for generating a detected output when the right dot, the left dot, the upper dot and the lower dot assume predetermined states determined in accordance with the characteristics of the dot-typed patterns, and means coupled to said shift register means and said detection means for obtaining in the same clock timing as the dot-typed patterns a logical sum of said one dot and said detected output of said detection means so as to provide restored patterns.
Claim 5
Dependent Claim
48 words
A restoration system according to claim 2, in which said detection means comprises a first AND circuit for providing a logical product of said right dot and said left dot, and a second AND circuit for providing a logical product of said upper dot and said lower dot.
Claim 6
Dependent Claim
80 words
A restoration system according to claim 2, in which said detection means comprises a first AND circuit for providing a logical product of said right dot and said left dot, a third AND circuit for providing a logical product of said upper dot, said lower dot and one of said right and left dots, and a fourth AND circuit for providing a logical product of said upper dot, said lower dot and the other of said right and left dots.
Claim 7
Dependent Claim
80 words
A restoration system according to claim 2, in which said detection means comprises a second AND circuit for providing a logical product of said upper dot and said lower dot, a fifth AND circuit for providing a logical product of said right dot, said left dot and one of said upper and lower dots, and a sixth AND circuit for providing a logical product of said right dot, said left dot and the other of said upper and lower dots.
Claim 8
Dependent Claim
112 words
A restoration system according to claim 2, in which said detection means comprises a sixth AND circuit for providing a logical product of said right dot, said left dot and the other of said upper and lower dots, a fourth AND circuit for providing a logical product of said upper dot, said lower dot and the other of said right and left dots, a fifth AND circuit for providing a logical product of said right dot, said left dot and one of said upper and lower dots, and a third AND circuit for providing a logical product of said upper dot, said lower dot and one of said right and left dots.