US3781831A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Read only memory utilizing floating gate transistors and method of programming
Assignee: General Electric Co
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Filing: 1972-06-30
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Granted: 1973-12-25
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Expires: 1992-06-30
Abstract
Abstract A read only memory cell comprising a floating gate field effect transistor as the storage element is disclosed. Low operating voltages are used by including metal-oxide-semiconductor (MOS) varactors in the cell, enabling one to selectively induce avalanche injection for storing charge at selected bit sites.
Inventors
- 👤 C Neugebauer
- 👤 J Mundy
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 09:12
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/04; G11C16/0408; G11C16/0433
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
74 words
A memory cell comprising: a floating gate field effect transistor; a voltage variable capacitor comprising a gate electrode and a drain electrode, said gate electrode being connected to the drain of said floating gate field effect transistor; and at least two access lines, one of said access lines connected to the source of said floating gate field effect transistor, a second of said access lines connected to the drain of said voltage variable capacitor.
Claim 2
Dependent Claim
74 words
A memory cell comprising: a floating gate field effect transistor; a voltage variable capacitor comprising a gate electrode and a drain electrode, said gate electrode being connected to the drain of said floating gate field effect transistor; and at least two access lines, one of said access lines connected to the source of said floating gate field effect transistor, a second of said access lines connected to the drain of said voltage variable capacitor.
Claim 3
Dependent Claim
48 words
The memory cell as set forth in claim 1 and further comprising: means for raising said voltage variable capacitor to a high capacitance state to cause said voltage variable capacitor to couple signals from said second access line to the drain of said floating gate field effect transistor.
Claim 4
Dependent Claim
63 words
The memory cell as set forth in claim 2 wherein said means for raising said voltage variable capacitor to a high capacitance state comprises: third and fourth access lines; another field effect transistor having the gate thereof connected to said third access lines and the source-drain path thereof interconnecting the drain of said floating gate field effect transistor and said fourth access line.
Claim 5
Dependent Claim
28 words
The memory cell as set forth in claim 3 wherein said floating gate field effect transistor further comprises an erase gate overlying a portion of said floating gate.
Claim 6
Dependent Claim
28 words
The memory cell as set forth in claim 1 wherein said floating gate field effect transistor further comprises an erase gate overlying a portion of said floating gate.
Claim 7
Independent Claim
103 words
A method for selectively transferring charge to floating gate storage nodes in a memory array comprising memory cells containing floating gate field effect transistors comprising the steps of: providing each memory cell with a voltage variable capacitor connected to the source-drain path of said floating gate field effect transistor; raising selected ones of said capacitors to the high capacitance state to cause a potential difference to exist across the selected capacitors; and applying a voltage less than the avalanche voltage of said floating gate field effect transistor to at least said selected capacitors to couple said voltage to the source-drain paths connected thereto.
Claim 8
Independent Claim
103 words
A method for selectively transferring charge to floating gate storage nodes in a memory array comprising memory cells containing floating gate field effect transistors comprising the steps of: providing each memory cell with a voltage variable capacitor connected to the source-drain path of said floating gate field effect transistor; raising selected ones of said capacitors to the high capacitance state to cause a potential difference to exist across the selected capacitors; and applying a voltage less than the avalanche voltage of said floating gate field effect transistor to at least said selected capacitors to couple said voltage to the source-drain paths connected thereto.
Claim 9
Dependent Claim
43 words
The method as set forth in claim 6 wherein said potential difference is equal to or greater than approximateLy one-half the voltage necessary for avalanche injection and said voltage is equal to or less than approximately one-half the voltage necessary for avalanche injection.
Claim 10
Dependent Claim
44 words
The method as set forth in claim 6 wherein said activating and applying steps are repeated until the selected floating gates are sufficiently charged to induce a channel to form between the source and drain electrodes of the selected floating gate field effect transistors.
References Cited (Backward Citations)
US3500142A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-12-24 | 1977-06-25 | 1977-12-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-12-24 | 1981-06-25 | 1981-12-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-12-24 | 1985-06-25 | 1985-12-25 | $7700.00 | Window Closed / Lapsed |