Apparatus for propagating internal logic gate faults in a digital logic simulator

Claim 1

An improved digital computer of the type where circuitry is internally connected when a stored list of instructions is processed by a central processing unit, said computer being used for simulating the propagation of internal faults of a logic device on a feedback loop, wherein the improvement comprises; 1. a first storage circuit for a plurality of signals, said signals representing fault lists for each input terminal of said logic device, said fault lists consisting of external faults, and internal faults of said logic device which appear as inputs to the device through a feedback loop; 2. a second storage circuit for a sequence of signals, each signal corresponding to the error-free input logic value of one of the input terminals of the logic device; 3. a third storage circuit for storing the error-free output value of the logic device which results when said error-free input logic values are applied to the device; 4. a fourth storage circuit for a plurality of signal sequences representing input logic values and corresponding signals representing error-free output logic values, internal faults, and logical effects values for said logic device, said input logic values comprising every combination of logic values possible on the leads of said logic device; 5. a signal control circuit responsive to said first storage circuit, said control circuit testing in turn each fault list corresponding to said input terminal, then examining in turn each internal fault in said fault list, then transferring control to, a. a generating circuit for replicating the sequence of signals stored in said second storage circuit, except for the complimenting of the signal corresponding to the said input terminal under test, and then to b. a first testing circuit for comparing the signal sequence generated by said generating circuit with said plurality of signals sequences stored in said fourth storage circuit until an exact match occurs, and then to c. a signal output circuit responsive to said matching signal sequence of said first testing circuit and said internal fault of said signal control circuit for the extraction of said logical effect signal corresponding to said matching signal sequence and said internAl fault from said fourth storage circuit, and then to d. a second testing circuit for comparing said extracted logical effect signal of said signal output circuit with said error-free output value of said third storage circuit, said second testing circuit producing a test signal of a first type if said logical effect signal and said error-free output value are the same, and producing a test signal of a second type otherwise, and then to e. an output storage circuit for storing said internal fault if said test signal is of said second type.