US3768080A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Device for address translation
Assignee: International Business Machines Corp
•
Filing: 1972-01-20
•
Granted: 1973-10-23
•
Expires: 1992-01-20
Abstract
Abstract In a microprogrammed processor, a pair of register means and an associative store are arranged to eliminate the need to translate, for each microinstruction, a logical address to a real address to access main storage. Translation is required only once for each program or machine level (macro) instruction. The real addresses of the first bytes of the current instruction and its operand(s) are stored in a first one of the register means and are normally incremented to access the remainder of the instruction and operands byte-by-byte. In addition, the first register means and incrementer can be used to access sequentially stored instructions in a program sequence without address translation. When a page boundary is crossed during said incrementing, the logical page address of the current instruction or operand (which is at the boundary) is read from the second register means and is incremented to form the logical address of the next sequential page. This new logical address is searched in the associative array. If a match occurs, the new logical address is stored in the second register means, and the corresponding real address is stored in the first register means. This hardware translate means significantly reduces translate time.
Inventors
- 👤 K Boger
- 👤 H Geng
- 👤 V Gotze
- 👤 J Hajdu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 19:37
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/10; G06F12/1027; G06F12/1036; G06F2212/00; G06F2212/65; G06F2212/655
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
228 words
In a data processing system of the type wherein logical page addresses are translated by means of main storage table look-up into real block addresses for accessing operands and instructions from main storage, wherein the most recently used ones of the logical page addresses and their corresponding real block addresses are stored in an associative storage for rapid translation on subsequent reuse, and wherein means including a first incrementer is normally effective for updating current real addresses to sequentially access instructions and operands or portions thereof from main storage for processing, in combination therewith a first register means for storing simultaneously the real addresses of the current instruction and its operands and adapted to supply said addresses for accessing main storage, means including said first incrementer effective for updating in word and sub-word address increments each address in the first register means after it is supplied for accessing main storage and for returning the updated address to the first register means, an additional register means for storing the logical page address corresponding to each real address in the first register means, and means effective, when the first register means supplies an address to access main storage which address is the last address in a block, for transferring the logical and real address of the next page and its corresponding block to the second and first register means respectively.
Claim 2
Dependent Claim
228 words
In a data processing system of the type wherein logical page addresses are translated by means of main storage table look-up into real block addresses for accessing operands and instructions from main storage, wherein the most recently used ones of the logical page addresses and their corresponding real block addresses are stored in an associative storage for rapid translation on subsequent reuse, and wherein means including a first incrementer is normally effective for updating current real addresses to sequentially access instructions and operands or portions thereof from main storage for processing, in combination therewith a first register means for storing simultaneously the real addresses of the current instruction and its operands and adapted to supply said addresses for accessing main storage, means including said first incrementer effective for updating in word and sub-word address increments each address in the first register means after it is supplied for accessing main storage and for returning the updated address to the first register means, an additional register means for storing the logical page address corresponding to each real address in the first register means, and means effective, when the first register means supplies an address to access main storage which address is the last address in a block, for transferring the logical and real address of the next page and its corresponding block to the second and first register means respectively.
Claim 3
Dependent Claim
109 words
The combination set forth in claim 1 wherein the last-mentioned means comprises means in the first incrementer for producing a carry signal when a block boundary is crossed, means including a second incrementer for incrementing the logical page address of the additional register means during each main memory accesss, means effective only in response to a carry signal for searching the associative storage for a logical address equal in value tO that of said incremented logical page address, and means responsive to a match during said search for storing the incremented logical page address in the additional register means and the corresponding real address in the first register means.
Claim 4
Dependent Claim
148 words
In a data processing system of the type wherein logical page addresses are translated by means of main storage table look-up into real block addresses for accessing operands and instructions from main storage, wherein the most recently used ones of the logical page addresses and their corresponding real block addresses are stored in an associative storage for rapid translation on subsequent reuse, and wherein means including an incrementer is normally effective for updating current real addresses to sequentially access instructions and operands from main storage for processing, in combination therewith a register means for storing simultaneously the real addresses of the current instruction and its operands and adapted to supply said addresses for accessing main storage, and said incrementer effective for updating each address in the register means as each address is supplied for accessing consecutive portions of each instruction operand without table look-up or associative store translation.
Claim 5
Dependent Claim
148 words
In a data processing system of the type wherein logical page addresses are translated by means of main storage table look-up into real block addresses for accessing operands and instructions from main storage, wherein the most recently used ones of the logical page addresses and their corresponding real block addresses are stored in an associative storage for rapid translation on subsequent reuse, and wherein means including an incrementer is normally effective for updating current real addresses to sequentially access instructions and operands from main storage for processing, in combination therewith a register means for storing simultaneously the real addresses of the current instruction and its operands and adapted to supply said addresses for accessing main storage, and said incrementer effective for updating each address in the register means as each address is supplied for accessing consecutive portions of each instruction operand without table look-up or associative store translation.
Claim 6
Dependent Claim
35 words
The combination set forth in claim 3 wherein the incrementer is rendered effective to update instruction addresses in the register means to access instructions in a program sequence without table look-up or associative store translation.
Claim 7
Dependent Claim
141 words
In a virtual memory data processing system wherein logical addresses supplied by a program are first translated to real addresses for accessing data operands and program instructions in a main storage portion of the system for processing, the combination comprising a first register means for storing simultaneously the real addresses of the current instruction and its operands and adapted to supply said addresses for accessing main storage, means including translation means for transferring into the register means the real addresses of a first instruction in a sequence and its operands, and a first modifier circuit thereafter effective for incrementing the address value of each real address in the first register means in response to the real address being supplied to the main storage address register to access an operand or instruction, thereby forming a sequence of real addresses without further translation.
Claim 8
Dependent Claim
141 words
In a virtual memory data processing system wherein logical addresses supplied by a program are first translated to real addresses for accessing data operands and program instructions in a main storage portion of the system for processing, the combination comprising a first register means for storing simultaneously the real addresses of the current instruction and its operands and adapted to supply said addresses for accessing main storage, means including translation means for transferring into the register means the real addresses of a first instruction in a sequence and its operands, and a first modifier circuit thereafter effective for incrementing the address value of each real address in the first register means in response to the real address being supplied to the main storage address register to access an operand or instruction, thereby forming a sequence of real addresses without further translation.
Claim 9
Dependent Claim
147 words
The combination set forth in claim 5 further comprising an associative storage means for storing a group of most recently used logical addresses and their corresponding real addresses, an additional register means for storing the logical page address corresponding to each real address in the first register means, means for reading out and incrementing each logical page address from the additional register means when its corresponding real address is supplied from the first register means, means in the first modifier circuit responsive to the crossing of a page boundary in an address supplied from the first register means for searching the associative storage means for a logical page address corresponding to the incremented logical page address, and means responsive to a match in the associative storage means for storing the incremented logical page address and its corresponding real address in the additional and first register means respectively.
References Cited (Backward Citations)
US3444525A
Cited
US3505647A
Cited
US3469241A
Cited
US3569938A
Cited
US3599176A
Cited
US3614746A
Cited
US3541529A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-10-22 | 1977-04-23 | 1977-10-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-10-22 | 1981-04-23 | 1981-10-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-10-22 | 1985-04-23 | 1985-10-23 | $7700.00 | Window Closed / Lapsed |