Automatic signal acquisition means for phase-lock loop with anti- sideband lock protection

Claim 2

In a phase-lock loop receiver for receiving an input signal, including a first signal multiplier having one input to which said input signal is applied and having a second input and an output, a loop filter connected to the output of said first signal multiplier for receiving the output signal thereof, a voltage controlled oscillator having an input connected to said loop filter for receiving the output signal thereof, and a ninety degree phase shift network connected between the output of said voltage controlled oscillator and the second input of said first signal multiplier, means for enabling said receiver to acquire said input signal over a wide frequency range comprising: a second signal multiplier having two inputs and an output, said input signal being applied to one of said second multiplier inputs, the output signal of said voltage controlled oscillator being connected to the second input of said second signal multiplier, a differentiating network connected to the output of said second signal multiplier, said second signal multiplier combines said input signal and the output signal of said voltage controlled oscillator, a third multiplier connected to said differentiating network and to said first signal multiplier for receiving the output signal of said differentiating network and the output signal of said first signal multiplier, a summing network connected to said third multiplier and to said first signal multiplier for receiving the multiplied output of said third multiplier and the output of said first signal multiplier, and means for supplying the output signal of said summing network to said loop filter.

Claim 3

The phase-lock loop receiver according to claim 1 wherein low pass filters are connected respectively in the output circuits of said first signal multiplier and said second signal multiplier for eliminating higher frequency signal components.

Claim 4

The phase-lock loop receiver according to claim 2 wherein an integrating network is connected between the input to said third multiplier and the output of said first signal multiplier beyond the connection to said summing network.

Claim 5

A phase-lock loop receiver and signal acquisition aid circuit for receiving periodic signals comprising a first signal multiplier having two inputs and an output for producing an output signal corresponding to the product of its inputs, means for connecting a periodic signal to be received to one of the two inputs of said first signal multiplier, an oscillator having an input and an output and developing an output frequency which is dependent on its input voltage, a first phase shift network connected between the output of said oscillator and the other of the two inputs of said first signal multiplier, a first low pass filter connected to the output of said first signal multiplier for removing higher frequency components resulting from the product of the two inputs to said first signal multiplier, a summing network having two inputs, means for connecting the output of said first low pass filter to one of the two inputs of said summing network, the output of said first low pass filter being the loop control signal when the loop is in phase lock, a loop filter, means for connecting the output of said summing network to said loop filter, means for connecting the output of said loop filter to the input of said oscillator, a second signal multiplier having two inputs and an output for producing an output corresponding to the product of its inputs, means for connecting said periodic signal to be received to one of the two inputS of said second signal multiplier, means for connecting the output of said oscillator to the other of the two inputs of said second signal multiplier, a second low pass filter connected to the output of said second signal multiplier for removing higher frequency components resulting from the product of the two inputs to said second signal multiplier, a third multiplier having two inputs and an output, means providing a first signal path from said first low pass filter to one of the two inputs of said third multiplier, means providing a second signal path from said second low pass filter to the second of the two inputs of said third multiplier, means associated with said first and said second signal paths for shifting the relative phases of the signals at the two inputs of said third multiplier to a phase condition of one of substantially in phase or substantially one-hundred eighty degrees out of phase, said associated means developing a signal factor whose magnitude varies in proportion to the magnitude of the difference of said received signal frequency and said oscillator frequency and whose sign depends upon whether the frequency of the received signal is greater or lesser than the frequency of said oscillator, and means for connecting the output of said third multiplier to the second input of said summing network.

Claim 6

A phase-lock loop receiver and signal acquisition aid circuit for receiving periodic signals comprising a first signal multiplier having two inputs and an output for producing an output signal corresponding to the product of its inputs, means for connecting a periodic signal to be received to one of the two inputs of said first signal multiplier, an oscillator having an input and an output and developing an output frequency which is dependent on its input voltage, a first phase shift network connected between the output of said oscillator and the other of the two inputs of said first signal multiplier, a first low pass filter connected to the output of said first signal multiplier for removing higher frequency components resulting from the product of the two inputs to said first signal multiplier, a summing network having two inputs, means for connecting the output of said first low pass filter to one of the two inputs of said summing network, the output of said first low pass filter being the loop control signal when the loop is in phase lock, a loop filter, means for connecting the output of said summing network to said loop filter, means for connecting the output of said loop filter to the input of said oscillator, a second signal multiplier having two inputs and an output for producing an output corresponding to the product of its inputs, means for connecting said periodic signal to be received to one of the two inputS of said second signal multiplier, means for connecting the output of said oscillator to the other of the two inputs of said second signal multiplier, a second low pass filter connected to the output of said second signal multiplier for removing higher frequency components resulting from the product of the two inputs to said second signal multiplier, a third multiplier having two inputs and an output, means providing a first signal path from said first low pass filter to one of the two inputs of said third multiplier, means providing a second signal path from said second low pass filter to the second of the two inputs of said third multiplier, means associated with said first and said second signal paths for shifting the relative phases of the signals at the two inputs of said third multiplier to a phase condition of one of substantially in phase or substantially one-hundred eighty degrees out of phase, said associated means developing a signal factor whose magnitude varies in proportion to the magnitude of the difference of said received signal frequency and said oscillator frequency and whose sign depends upon whether the frequency of the received signal is greater or lesser than the frequency of said oscillator, and means for connecting the output of said third multiplier to the second input of said summing network.

Claim 7

The phase-lock loop receiver and signal acquisition aid circuit according to claim 4 wherein said first phase shift network comprises a lag network of substantially 90*, and said associated means comprises a lead network of substantially ninety degrees in said second signal path.

Claim 8

The phase-lock loop receiver and signal acquisition aid circuits according to claim 5 wherein said lead network comprises a differentiating circuit including a series capacitor and a shunt resistor.

Claim 9

The phase-lock loop receiver and signal acquisition aid circuit according to claim 4 wherein said first phase shift network comprises a lag network of substantially 90*, and said associated means comprises a lag network of substantially ninety degrees in said first signal path.

Claim 10

The phase-lock loop receiver and signal acquisition aid circuit according to claim 7 wherein the lag network in said first signal path comprises an integrating circuit including a series resistor and a shunt capacitor.

Claim 11

The phase-lock loop receiver and signal acquisition aid circuit according to claim 4 wherein said first phase shift network comprises a lag network of substantially 90*, and said associated means comprises a lead network of less than ninety degrees in said second signal path and a lag network of less than 90* in said first signal path.