US3763474A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Program activated computer diagnostic system
Assignee: AT&T Inc
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Filing: 1971-12-09
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Granted: 1973-10-02
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Expires: 1991-12-09
Abstract
Abstract A hardware diagnostic system is utilized to gather data on the real-time operation of software programs in a multiprocessor computer system. The system is activated by request instructions planted in the processor''s programs at those locations which the programmer wishes to monitor. Upon detecting one of the request instructions, the system acts essentially independent of processor control to gather information concerning when and which processor acted upon the request instruction. The processing system continues its data processing while the diagnostic system handles the monitoring request.
Inventors
- 👤 R Freeman
- 👤 L Loporcaro
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 09:44
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/0703; G06F11/0706; G06F11/0721; G06F11/0724; G06F11/0751; G06F11/30; G06F11/34; G06F11/3409; G06F11/3466; G06F11/348; G06F11/3419; G06F11/3495; G06F2201/00; G06F2201/86; G06F2201/88
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
310 words
In a data processing system comprising a plurality of data processing units for executing instructions, certain of said instructions having a data field, an operation code field and an address field; an auxiliary circuit arrangement for providing information concerning the execution of preselected ones of said certain instructions by said processing units comprising, a register circuit, a comparator circuit, a multiplexer scanner circuit Adapted for connection to each of said data processing units for receiving each of said certain instructions as it is being executed by any of said data processing units, and connected to said register circuit for conveying the data field of a received certain instruction to a first distinct portion of said register, and also connected to said comparator circuit for conveying the address field of said received certain instruction to said comparator circuit, an encoder circuit responsive to said scanner circuit and connected to said register circuit for generating processing unit identity information specifying the identity of the processing unit from which said certain instruction is received, and for conveying the generated processing unit identity information to a second distinct portion of said register circuit, said comparator circuit for comparing the address field of said received certain instruction with a predetermined address identifying said preselected ones of said certain instructions and for generating a first signal when a match occurs, a timer circuit connected to said comparator circuit and responsive to said first signal for specifying real-time indicia and also connected to said register circuit for conveying said specified real-time indicia to a third distinct portion of said register circuit, an address generator circuit responsive to said first signal for generating an address, and means responsive to said first signal and controlled by said address generator circuit for storing the contents of said register circuit at the location in a memory identified by said generated address.
Claim 2
Dependent Claim
310 words
In a data processing system comprising a plurality of data processing units for executing instructions, certain of said instructions having a data field, an operation code field and an address field; an auxiliary circuit arrangement for providing information concerning the execution of preselected ones of said certain instructions by said processing units comprising, a register circuit, a comparator circuit, a multiplexer scanner circuit Adapted for connection to each of said data processing units for receiving each of said certain instructions as it is being executed by any of said data processing units, and connected to said register circuit for conveying the data field of a received certain instruction to a first distinct portion of said register, and also connected to said comparator circuit for conveying the address field of said received certain instruction to said comparator circuit, an encoder circuit responsive to said scanner circuit and connected to said register circuit for generating processing unit identity information specifying the identity of the processing unit from which said certain instruction is received, and for conveying the generated processing unit identity information to a second distinct portion of said register circuit, said comparator circuit for comparing the address field of said received certain instruction with a predetermined address identifying said preselected ones of said certain instructions and for generating a first signal when a match occurs, a timer circuit connected to said comparator circuit and responsive to said first signal for specifying real-time indicia and also connected to said register circuit for conveying said specified real-time indicia to a third distinct portion of said register circuit, an address generator circuit responsive to said first signal for generating an address, and means responsive to said first signal and controlled by said address generator circuit for storing the contents of said register circuit at the location in a memory identified by said generated address.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-10-01 | 1977-04-02 | 1977-10-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-10-01 | 1981-04-02 | 1981-10-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-10-01 | 1985-04-02 | 1985-10-02 | $7700.00 | Window Closed / Lapsed |