US3763470A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Circuit arrangement for error detection in data processing systems
Assignee: International Business Machines Corp
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Filing: 1972-01-20
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Granted: 1973-10-02
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Expires: 1992-01-20
Abstract
Abstract In a data processing system, a first processing unit is connected to several other processing units by one transfer bus each for the two directions of transmission, a circuit arrangement for error detection being associated with the transfer lines. The first unit comprises a check character generator generating a parity check character both for the information to be transferred from the first processing unit to the further processing units and from the further processing units to the first processing unit. The transfer lines of both directions are provided with a common transfer path, by means of which the parity check characters generated by the check character generator are transferred from the first unit to the further units. Each of the further units comprises a check circuit connected to the two transfer buses and the check character transfer path and checking the correctness of the transferred information for both directions of transmission.
Inventors
- 👤 H Geng
- 👤 J Hajdu
- 👤 P Skuin
- 👤 E Vogt
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-22 21:44
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/08; G06F11/10; H; H04; H04L; H04L1/00; H04L1/004; H04L1/0041; H04L1/0056; H04L1/0061; H04L1/0063; H04L2001/0092; H04L2001/0094
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
197 words
In a data processing system of the type in which at least first and second processing units include first and second output means adapted to receive information bit groups produced in the first and second units resPectively and include first and second input means, and in which first and second buses respectively connect the first output means to the second input means and the second output means to the first input means for the transfer of information bit groups between the units, an error detection circuit comprising a common parity bit generator in the first unit coupled to the first output means and to the second bus generating a parity bit for information bit groups transferred from the first unit to the second unit and from the second unit to the first unit, a common parity bit transfer path, said common path being connected to the generator to transfer the parity bits generated by the generator from the first to the second unit, and a check circuit in the second unit connected to the two buses and to the common transfer path for checking the correctness of the transmitted information bit groups for both directions of transmission.
Claim 2
Dependent Claim
197 words
In a data processing system of the type in which at least first and second processing units include first and second output means adapted to receive information bit groups produced in the first and second units resPectively and include first and second input means, and in which first and second buses respectively connect the first output means to the second input means and the second output means to the first input means for the transfer of information bit groups between the units, an error detection circuit comprising a common parity bit generator in the first unit coupled to the first output means and to the second bus generating a parity bit for information bit groups transferred from the first unit to the second unit and from the second unit to the first unit, a common parity bit transfer path, said common path being connected to the generator to transfer the parity bits generated by the generator from the first to the second unit, and a check circuit in the second unit connected to the two buses and to the common transfer path for checking the correctness of the transmitted information bit groups for both directions of transmission.
Claim 3
Dependent Claim
114 words
The system set forth in claim 1 further comprising at least one additional first processing unit, each additional unit having a respective parity bit generator and each having an input means coupled to the second bus and an output means coupled to the second input means by a respective first bus for two way information transfer, an additional parity bit path for each additional first unit interconnecting a respective parity bit generator and said check circuit in the second unit, and means in each first unit connected to the second bus and controlled by information bits thereon from the second unit for selectively rendering the first units active for transmission with the second unit.
Claim 4
Dependent Claim
21 words
The system set forth in claim 2 further comprising means coupling all buses to the check circuit of the second unit.
Claim 5
Dependent Claim
131 words
The system set forth in claim 1 further comprising at least one additional first processing unit, each having a respective parity bit generator and each having an input means coupled to the second bus and an output means coupled to the second input means by a respective first bus for two way information transfer, logic means in each first unit connected to the second bus and responsive to information bits thereon for connecting the respective generator to said check circuit in the second unit by way of the common parity bit transfer path, and means in each first unit including said logic means connected to the second bus and controlled by information bits thereon from the second unit for selectively rendering the first units active for transmission with the second unit.
Claim 6
Dependent Claim
21 words
The system set forth in claim 4 further comprising means coupling all buses to the check circuit of the second unit.
Claim 7
Dependent Claim
65 words
The system set forth in claim 4 wherein the logic means includes interconnection paths between each first unit for extending the common parity bit path to each first unit, and a pair of gating circuits in each first unit interposed within said interconnection paths and controlled by the second unit for coupling the parity bit generator of only a selected unit to the common path.
Claim 8
Dependent Claim
81 words
The system set forth in claim 1 wherein information is transferred simultaneously in both directions between said units, said combination further comprising means coupling the generator to the first output to receive a parity bit associated with information leaving the first unit for the second unit and to the second bus to receive information being received simultaneously in the first unit from the second unit, said generator producing parity bits in response to said coupled check data and simultaneously received information.
Claim 9
Dependent Claim
201 words
In a data processing system of the type in which at least first and second processing units include first and second output means adapted to receive information bit groups produced in the first and second units respectively and include first and second input means, and in which first and second buses respectively connect the First output means to the second input means and the second output means to the first input means for the transfer of information bit groups between the units, an error detection circuit comprising a check character generator in the first unit coupled to the first output means and to the second bus generating a check character for information bit groups transferred simultaneously from the first unit to the second unit and from the second unit to the first unit, a common check character transfer path, said common path being connected to the generator to transfer the check characters generated by the check character generator from the first to the second unit, and a check circuit in the second unit connected to the two buses and to the common check character transfer path for checking the correctness of the transmitted information bit groups for both directions of transmission.
Claim 10
Dependent Claim
201 words
In a data processing system of the type in which at least first and second processing units include first and second output means adapted to receive information bit groups produced in the first and second units respectively and include first and second input means, and in which first and second buses respectively connect the First output means to the second input means and the second output means to the first input means for the transfer of information bit groups between the units, an error detection circuit comprising a check character generator in the first unit coupled to the first output means and to the second bus generating a check character for information bit groups transferred simultaneously from the first unit to the second unit and from the second unit to the first unit, a common check character transfer path, said common path being connected to the generator to transfer the check characters generated by the check character generator from the first to the second unit, and a check circuit in the second unit connected to the two buses and to the common check character transfer path for checking the correctness of the transmitted information bit groups for both directions of transmission.
Claim 11
Dependent Claim
137 words
The system set forth in claim 8 further comprising at least one additional first processing unit, each having an input means connected to the second bus, each having a respective check character generator and a respective common check character transfer path and each having an output means coupled to the second input means by a respective first bus, logic means in each first unit connected to the second bus and responsive to information bits thereon for connecting the respective check character generator to said check circuit in the second unit by way of the common check character transfer path, and means in each first unit including said logic means connected to the second bus and controlled by information bits thereon from the second unit for selectively rendering the first units active for transmission with the second unit.
References Cited (Backward Citations)
US3473150A
Cited
US3525077A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-10-01 | 1977-04-02 | 1977-10-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-10-01 | 1981-04-02 | 1981-10-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-10-01 | 1985-04-02 | 1985-10-02 | $7700.00 | Window Closed / Lapsed |