US3761893A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Digital computer
Assignee: Modicon Corp
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Filing: 1970-07-02
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Granted: 1973-09-25
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Expires: 1990-07-02
Abstract
Abstract Hardware registers which are addressed in the same manner as the main core memory and exchange data with external devices. The computer has no dedicated registers used as the accumulator, program counter and program counter save. Rather, addressed registers in the main core memory are used for these functions. Preferably, there are a plurality of each group comprising a dedicated computational machine. The computational machine which is being operated is specified by a dedicated machine pointer register. Mass memory, additional computers, as well as input and output devices may be connected to the addressed hardware registers to provide unlimited system expansion. Program instructions may be placed in an addressed hardware register in response to external events. The main core memory provided contains all possible addresses in the ten bit address word of the computer. When an addressed hardware register is connected to the computer, it becomes responsive to the central processing unit, rather than the identically addressed core position. The core position is reactivated when the hardware register is disabled by events either external or internal to the computer. This dual addressing scheme is controlled by two priority levels. All address registers and all dedicated machine registers are connected in parallel to a half duplex transfer bus which provides for transfers between any registers connected thereto under control of a central processing unit. All cycles of the computer are identical and comprise three timing states.
Inventors
- 👤 R Morley
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-22 20:20
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/46; G06F9/48; G06F9/4806; G06F9/4812; G06F9/30; G06F9/30098; G06F9/30101; G06F9/3012; G06F9/30138; G06F9/4843
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
288 words
A digital computer comprising: A. a data transfer bus; B. a central processing unit connected to the data transfer bus including means for addressing storage locations and means for receiving and processing data transferred over the data transfer bus from addressed storage locations; C. multi address memory means comprising 1. one addressable storage location for each address which may be addressed according to the word length provided for addressing in the computer and further comprising 2. at least one additional addressable storage location, each additional addressable storage locAtion having an address different from each other additional addressable storage location and each additional addressable storage location having one of the addresses which may be addressed according to the word length providing for addressing in the computer, whereby at least two addressable storage locations of the multi address memory means have an identical address; and D. address recognition and response means associated with said multi address memory, said address recognition and response means comprising: 1. address recognition means associated with all addressable storage locations for connecting any one of the addressable storage locations to the data transfer bus in response to the address of the addressable storage location; 2. priority assertion means associated with the additional addressable storage locations for asserting a priority response level signal when one of the additional addressable storage locations is addressed; and 3. priority response means associated with the remaining addressable storage locations for inhibiting connection of the addressable storage location having the address identical to the address of the addressed additional addressable storage location to the data transfer bus in response to the asserted priority response level signal, whereby only the addressed additional addressable storage location is accessed in response to an identical address.
Claim 2
Dependent Claim
288 words
A digital computer comprising: A. a data transfer bus; B. a central processing unit connected to the data transfer bus including means for addressing storage locations and means for receiving and processing data transferred over the data transfer bus from addressed storage locations; C. multi address memory means comprising 1. one addressable storage location for each address which may be addressed according to the word length provided for addressing in the computer and further comprising 2. at least one additional addressable storage location, each additional addressable storage locAtion having an address different from each other additional addressable storage location and each additional addressable storage location having one of the addresses which may be addressed according to the word length providing for addressing in the computer, whereby at least two addressable storage locations of the multi address memory means have an identical address; and D. address recognition and response means associated with said multi address memory, said address recognition and response means comprising: 1. address recognition means associated with all addressable storage locations for connecting any one of the addressable storage locations to the data transfer bus in response to the address of the addressable storage location; 2. priority assertion means associated with the additional addressable storage locations for asserting a priority response level signal when one of the additional addressable storage locations is addressed; and 3. priority response means associated with the remaining addressable storage locations for inhibiting connection of the addressable storage location having the address identical to the address of the addressed additional addressable storage location to the data transfer bus in response to the asserted priority response level signal, whereby only the addressed additional addressable storage location is accessed in response to an identical address.
Claim 3
Dependent Claim
28 words
priority assertion means associated with the additional addressable storage locations for asserting a priority response level signal when one of the additional addressable storage locations is addressed; and
Claim 4
Dependent Claim
28 words
priority assertion means associated with the additional addressable storage locations for asserting a priority response level signal when one of the additional addressable storage locations is addressed; and
Claim 5
Dependent Claim
86 words
at least one additional addressable storage location, each additional addressable storage locAtion having an address different from each other additional addressable storage location and each additional addressable storage location having one of the addresses which may be addressed according to the word length providing for addressing in the computer, whereby at least two addressable storage locations of the multi address memory means have an identical address; and D. address recognition and response means associated with said multi address memory, said address recognition and response means comprising:
Claim 6
Dependent Claim
86 words
at least one additional addressable storage location, each additional addressable storage locAtion having an address different from each other additional addressable storage location and each additional addressable storage location having one of the addresses which may be addressed according to the word length providing for addressing in the computer, whereby at least two addressable storage locations of the multi address memory means have an identical address; and D. address recognition and response means associated with said multi address memory, said address recognition and response means comprising:
Claim 7
Dependent Claim
76 words
A digital computer as defined in claim 1, wherein at least a portion of the multi address memory comprises addressable external registers connected to the data transfer bus and further comprising: E. external devices connected to the external registers which transfer data to and from the external registers in real time whereby when the addressable storage location comprising the external register is addressed and connected to the data transfer bus, the latest updated information is available.
Claim 8
Dependent Claim
62 words
priority response means associated with the remaining addressable storage locations for inhibiting connection of the addressable storage location having the address identical to the address of the addressed additional addressable storage location to the data transfer bus in response to the asserted priority response level signal, whereby only the addressed additional addressable storage location is accessed in response to an identical address.
Claim 9
Dependent Claim
62 words
priority response means associated with the remaining addressable storage locations for inhibiting connection of the addressable storage location having the address identical to the address of the addressed additional addressable storage location to the data transfer bus in response to the asserted priority response level signal, whereby only the addressed additional addressable storage location is accessed in response to an identical address.
Claim 10
Dependent Claim
65 words
The digital computer as defined in claim 3, wherein the additional addressable storage locations of the multi address memory comprise addressable external registers connected to the data transfer bus and the remaining portion of said multi address memory comprises a random access memory having one storage location for each address which may be addressed according to the word length provided for addressing in the computer.
Claim 11
Dependent Claim
67 words
A digital computer as defined in claim 3, wherein at least one of said addressable external hardware registers further comprises externally controlled means for inhibiting the address recognition and response means associated with the addressable external register, whereby the addressable external register is not accessed in response to its address and whereby the other storage location having the identical address is accessed in response to the address.
Claim 12
Dependent Claim
78 words
A digital computer as defined in claim 3, wherein said central processing unit further comprises means for partially decoding the addresses of said addressable external registers and providing partially decoded address signals to said addressable external registers when one of the addressable external registers is addressed and wherein the address recognition and response means associated with the addressable external registers comprises means for recognizing and responding to the partially decoded address signal of each individual addressable external register.
Claim 13
Dependent Claim
204 words
A digital computer comprising: A. a data transfer bus; B. a central processing unit connected to the data transfer bus including means for addressing storage locations and means for receiving and processing data transferred over the data transfer bus from addressed storage locations; C. a random access memory connected to the data transfer bus through an associated memory buffer register, the random access memory having one storage location for each address which may be addressed according to the word length provided for addressing in said computer; D. at least one addreSsable external register connected to the data transfer bus, each external register having an address different from the addresses of all other external registers, and the same as the address of one storage location in the random access memory; E. priority assertion means associated with the addressable external registers for producing a priority signal when one of the addressable external registers is addressed by the central processing unit; and F. priority response means associated with the random access memory and associated memory buffer register for receiving the priority signal and in response thereto for inhibiting access to the storage location in the random access memory having the same address as the addressable external register.
Claim 14
Dependent Claim
204 words
A digital computer comprising: A. a data transfer bus; B. a central processing unit connected to the data transfer bus including means for addressing storage locations and means for receiving and processing data transferred over the data transfer bus from addressed storage locations; C. a random access memory connected to the data transfer bus through an associated memory buffer register, the random access memory having one storage location for each address which may be addressed according to the word length provided for addressing in said computer; D. at least one addreSsable external register connected to the data transfer bus, each external register having an address different from the addresses of all other external registers, and the same as the address of one storage location in the random access memory; E. priority assertion means associated with the addressable external registers for producing a priority signal when one of the addressable external registers is addressed by the central processing unit; and F. priority response means associated with the random access memory and associated memory buffer register for receiving the priority signal and in response thereto for inhibiting access to the storage location in the random access memory having the same address as the addressable external register.
Claim 15
Dependent Claim
50 words
A digital computer as defined in claim 6 further comprising: G. external devices connected to the external registers which transfer data to and from the external registers in real time, whereby when the external register is addressed and connected to the data transfer bus, the latest updated information is available.
Claim 16
Dependent Claim
151 words
A digital computer comprising: A. a data transfer bus; B. a central processing unit connected to the data transfer bus including means for addressing storage locations and means for receiving and processing data transferred over the data transfer bus from addressed storage locations; C. multi address memory means comprising addressable storage locations, at least some of which are contained in a random access memory connected to the data transfer bus through a memory buffer register and at least some of which comprise directly addressable external registers connected to the data transfer bus through address recognition and response means for accessing the addressable external registers in response to their addresses; D. external devices connected to the external registers which transfer data to and from the external registers in real time, whereby when the external registers are accessed, the latest updated information is exchangeable between the external devices and the central processing unit.
Claim 17
Dependent Claim
151 words
A digital computer comprising: A. a data transfer bus; B. a central processing unit connected to the data transfer bus including means for addressing storage locations and means for receiving and processing data transferred over the data transfer bus from addressed storage locations; C. multi address memory means comprising addressable storage locations, at least some of which are contained in a random access memory connected to the data transfer bus through a memory buffer register and at least some of which comprise directly addressable external registers connected to the data transfer bus through address recognition and response means for accessing the addressable external registers in response to their addresses; D. external devices connected to the external registers which transfer data to and from the external registers in real time, whereby when the external registers are accessed, the latest updated information is exchangeable between the external devices and the central processing unit.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-09-24 | 1977-03-26 | 1977-09-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-09-24 | 1981-03-26 | 1981-09-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-09-24 | 1985-03-26 | 1985-09-25 | $7700.00 | Window Closed / Lapsed |