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US3761882A
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Process control computer
Assignee: MICROFAST CONTROLS Corp A CORP OF
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Filing: 1971-12-01
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Granted: 1973-09-25
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Expires: 1991-12-01
Abstract
Abstract A solid state process control computer for continually controlling a plurality of outputs in dependence upon the conditions of a plurality of continually variable input parameters. The controller includes a memory capable of storing a large number of multi-bit words each comprising both an address and an instruction. The memory is scanned on a word-by-word basis at high speed. A central processing means is provided and a data input/output bus is connected both to the input and the output of the central processing means. As each word in the memory is scanned, the instruction portion of each scanned word selectively either enables the central processing means to receive data from input/output bus or it enables the input/output bus to receive data from the central processing means. The address portion of each scanned word in the memory operatively connects any one of a plurality of registers to the input/output bus. A register may either be connected so as to be responsive to an input parameter or it may be connected so as to control an output device. The memory comprises a matrix having a large plurality of intersections each including a fused diode. The placing of a word in the memory is accomplished by selectively open circuiting one or more of the fused diodes corresponding respectively to the different bits of each word in the memory.
Inventors
- 👤 P Bartlett
- 👤 D Henry
- 👤 T Murrell
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 01:28
CPC Classifications
G; G05; G05B; G05B19/00; G05B19/02; G05B19/04; G05B19/05; G05B2219/00; G05B2219/10; G05B2219/11; G05B2219/1127; G05B2219/1159; G05B2219/1168; G05B2219/13; G05B2219/13016; G05B2219/13128
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
182 words
A process control computer which is continuously responsive to a plurality of variable input parameters and continuously controls in accordance with such input parameters a plurality of output devices in combination, a plurality of registers, a read-only memory for storing a plurality of words each comprising an address and an instruction, means for continuously and repetitively scanning one at a time all the words stored in said memory, central processing means, a data input/output bus connected both to the input and output of said central processing means, first means responsive to the address portion of each scanned word in said memory for operatively connecting any one of said registers to said input/output bus, second means responsive to the instruction portion of each word scanned by said scanning means for selectively either enabling said central processing means to receive data from said input/output bus or to enable said input/output bus to receive data from said central processing means, and means connecting some of said registers to be responsive to said input parameters and for connecting others of said registers to said output devices.
Claim 2
Dependent Claim
182 words
A process control computer which is continuously responsive to a plurality of variable input parameters and continuously controls in accordance with such input parameters a plurality of output devices in combination, a plurality of registers, a read-only memory for storing a plurality of words each comprising an address and an instruction, means for continuously and repetitively scanning one at a time all the words stored in said memory, central processing means, a data input/output bus connected both to the input and output of said central processing means, first means responsive to the address portion of each scanned word in said memory for operatively connecting any one of said registers to said input/output bus, second means responsive to the instruction portion of each word scanned by said scanning means for selectively either enabling said central processing means to receive data from said input/output bus or to enable said input/output bus to receive data from said central processing means, and means connecting some of said registers to be responsive to said input parameters and for connecting others of said registers to said output devices.
Claim 3
Dependent Claim
109 words
The combination of claim 1 in which each of said registers which are connected to said output devices comprises a temporary storage register which is at any time responsive to data on said input/output bus subject only to its being selected by said first means in accordance with the address portion of a scanned memory word and also comprises a holding register whose condition continually governs the operated condition of the associated controlling device, and means for controlling said holding register to a condition in accordance with that of the respective temporary storage register only upon the completion of a scan of all the words in said read-only memory.
Claim 4
Dependent Claim
81 words
The combination of claim 2 which further includes a source of power at a predetermined frequency for operating said controlled devices, said register controlling means being responsive both to said power source and to said scanning means for controlling each holding register to a condition in accordance with that of the respective temporary storage register only when both the scan of the memory has been completed and the waveform of the voltage of said power source is substantially at zero amplitude.
Claim 5
Dependent Claim
44 words
The combination of claim 1 in which said read-only memory comprises a matrix of row and column buses, eaCh bit of each memory word being represented by the selective interconnection between a pair of said buses, a fused diode providing each such selective interconnection.
Claim 6
Dependent Claim
92 words
The combination of claim 1 in which said central processing means comprises first and second accumulator registers, logic means responsive to each memory word for forming a predetermined logic function with the data then stored in a first of said accumulator registers and data on said input/output bus, said logic means being further responsive to a predetermined instruction in a scanned memory word for leading data into either of said accumulator registers, and AND gate means receiving inputs from both said accumulator registers for at times placing data on said input/output bus.
Claim 7
Dependent Claim
98 words
The combination of claim 1 which includes a power source of a predetermined frequency for energizing said controlled devices, said registers which are connected to be responsive to said input parameters being responsive both to said first means and to said power source and also to said scanning means, each said last-named register being responsive to the occurrence of a peak in the amplitude of the waveform of voltage of said power source occurring prior to the beginning of each scan of said memory for controlling such register to be operated in accordance with the respective input parameter.
Claim 8
Dependent Claim
215 words
A process control computer which is continuously responsive to a plurality of variable input parameters and continuously controls, in accordance with such input parameters, a plurality of output devices comprising in combination, a plurality of input registers, and a plurality of output registers, a read-only memory for storing a plurality of words each comprising an address and an instruction, means for continuously and repetitively scanning one at a time all the words stored in said memory, and central processing means, including, a single bit accumulator register, first means responsive to the address portion of each scanned word in said memory, second means responsive to the instruction portion of each scanned word in said memory, first logic means, responsive to said second means, for placing in said accumulator a data bit from a particular input or output register as selected by said first means, second logic means, responsive to said second means, for performing a predetermined logic function with the single data bit then in said accumulator and the data then stored in a particular input or output register as selected by said first means, third logic means, responsive to said second means, for controlling a particular output register, as selected by said first means, in accordance with the data bit then stored in said accumulator.
Claim 9
Dependent Claim
215 words
A process control computer which is continuously responsive to a plurality of variable input parameters and continuously controls, in accordance with such input parameters, a plurality of output devices comprising in combination, a plurality of input registers, and a plurality of output registers, a read-only memory for storing a plurality of words each comprising an address and an instruction, means for continuously and repetitively scanning one at a time all the words stored in said memory, and central processing means, including, a single bit accumulator register, first means responsive to the address portion of each scanned word in said memory, second means responsive to the instruction portion of each scanned word in said memory, first logic means, responsive to said second means, for placing in said accumulator a data bit from a particular input or output register as selected by said first means, second logic means, responsive to said second means, for performing a predetermined logic function with the single data bit then in said accumulator and the data then stored in a particular input or output register as selected by said first means, third logic means, responsive to said second means, for controlling a particular output register, as selected by said first means, in accordance with the data bit then stored in said accumulator.
Claim 10
Dependent Claim
60 words
The apparatus of claim 7 in which said central processing means includes a second single-bit data storage register and means, responsive to said first and second means, for placing in said storage register a data bit representative of a particular input condition, and AND logic means responsive to both said accumulator and said storage register for controlling an output register.
Claim 11
Dependent Claim
31 words
The combination of claim 8 which further includes an input/output bus and multiplexer means controlled by said second means for, at times, operatively connecting a particular input register to said bus.
Claim 12
Dependent Claim
39 words
The apparatus of claim 9 in which the output of said accumulator is, at times, in response to said second means, connected to said bus and via said bus to a particular output register selected by said first means.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-09-24 | 1977-03-26 | 1977-09-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-09-24 | 1981-03-26 | 1981-09-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-09-24 | 1985-03-26 | 1985-09-25 | $7700.00 | Window Closed / Lapsed |