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US3761822A Expired / Lapsed US ⏱️ 0.0 years remaining

Multiple receiver selection system

Assignee: Pye Electronic Products Ltd
•
Filing: 1971-02-02
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Granted: 1973-09-25
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Expires: 1991-02-02
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Abstract

Abstract The invention provides apparatus for selecting from a plurality of receiving stations, each station simultaneously receiving radio frequency signals containing identical information, the signal with the best signal-noise ratio. At each receiving station a control signal is generated, the frequency of which is determined by the signal-noise ratio of the radio signal received by that station. These signals are fed from the respective receiving stations to a central control which monitors the incoming control signals and selects the signal with the best signal-noise ratio.

Inventors

  • 👤 J Richardson
  • 👤 Sharpe A Keith

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-23 10:13
CPC Classifications
H; H04; H04B; H04B7/00; H04B7/02; H04B7/04; H04B7/08; H04B7/0802; H04B7/0805; H04B7/0808

Claims Analysis

Total Claims: 5
Claim 1
Independent Claim 407 words
Apparatus for selecting the highest quality signal from a plurality of incoming identical signals, comprising input means for separately receiving said signal, means for providing each signal with an additional modulated carrier wave component related to the quality thereof, the frequencies of the quality signal component lying outside the frequency band of the received signal, first switching means for selecting said signals from said input means in sequence during successive scanning cycles, signal processing means for providing voltages representing the quality components of signals from said first switching means, control means for producing pulses from the highest voltage of said signal processing means during each scanning cycle, said control means comprising storage means for receiving the voltages from said signal processing means to produce pulses for voltage increases during each scanning cycle, generating means for producing continuous clock pulses, the time interval of each switching sequence being equal to the time interval between the clock pulses, scan control means to drive said first switching means in response to clock pulses from said generating means and produce pulses for discharging said storage means in response to said clock pulses and the pulses from said storage means, said scan control means comprising input means for receiving said clock pulses, a first binary counter connected to said input means for driving said first switching means, a gate connected to said input means for inverting said clock pulses, a second binary counter for receiving the output of said gate, an AND gate for receiving the outputs of said gate and said second binary counter to produce an output pulse for discharging said storage means at a time interval after the output pulse of said storage means equal to said scanning cycle, said second binary counters being reset by the output pulse of said storage means, the time interval between the initiation of the pulses from said storage means and the pulses from said scan control means being equal to the time interval of said cycle, and selection control means to drive said second switching means in response to the pulses of said storage means and said scan control means, said pulses corresponding with signals having the highest quality components, second switching means for selecting the highest quality signals from said input means during successive scanning cycles in response to the pulses of said control means, and filter means for passing said signals having no quality components from said second switching means.
Claim 2
Dependent Claim 407 words
Apparatus for selecting the highest quality signal from a plurality of incoming identical signals, comprising input means for separately receiving said signal, means for providing each signal with an additional modulated carrier wave component related to the quality thereof, the frequencies of the quality signal component lying outside the frequency band of the received signal, first switching means for selecting said signals from said input means in sequence during successive scanning cycles, signal processing means for providing voltages representing the quality components of signals from said first switching means, control means for producing pulses from the highest voltage of said signal processing means during each scanning cycle, said control means comprising storage means for receiving the voltages from said signal processing means to produce pulses for voltage increases during each scanning cycle, generating means for producing continuous clock pulses, the time interval of each switching sequence being equal to the time interval between the clock pulses, scan control means to drive said first switching means in response to clock pulses from said generating means and produce pulses for discharging said storage means in response to said clock pulses and the pulses from said storage means, said scan control means comprising input means for receiving said clock pulses, a first binary counter connected to said input means for driving said first switching means, a gate connected to said input means for inverting said clock pulses, a second binary counter for receiving the output of said gate, an AND gate for receiving the outputs of said gate and said second binary counter to produce an output pulse for discharging said storage means at a time interval after the output pulse of said storage means equal to said scanning cycle, said second binary counters being reset by the output pulse of said storage means, the time interval between the initiation of the pulses from said storage means and the pulses from said scan control means being equal to the time interval of said cycle, and selection control means to drive said second switching means in response to the pulses of said storage means and said scan control means, said pulses corresponding with signals having the highest quality components, second switching means for selecting the highest quality signals from said input means during successive scanning cycles in response to the pulses of said control means, and filter means for passing said signals having no quality components from said second switching means.
Claim 3
Dependent Claim 86 words
Apparatus as claimed in claim 1 wherein said signal processing means comprises a first filter means for passing quality components of each signal from said first switching means, said first filter means comprising a first amplifying means, a blocking capacitor, a plurality of parallel, capacitively coupleD resonant circuits, second amplifying means, and means for lowering the Q of said resonant circuit at times controlled by said clock pulses and discriminating means for providing voltage representing the quality components of each signal from said first filter means.
Claim 4
Dependent Claim 107 words
Apparatus as claimed in claim 1 wherein said storage means comprises means for charging a capacitor during sequence in said scanning cycle when the voltage of said signal processing means is higher than the voltage on said capacitor in the presence of a constant amplitude replica of said voltage of said signal processing means, means for maintaining the voltage of said capacitor constant when said constant amplitude replica of said signal processing means is absent, means for producing a pulse during the sequence of said scanning cycle when said capacitor is charging, and means for discharging said capacitor in response to pulses from said scan control means.
Claim 5
Dependent Claim 72 words
Apparatus as claimed in claim 2 wherein said means for lowering the Q of said first filter means comprise a monostable circuit triggered by said clock pulses to produce a train of pulses, and transistor switching devices positioned between the coupling of said parallel resonant circuits and responsive to said train of pulses to provide critical damping to said resonant circuits prior to the arrival of said quality components of said signals.

References Cited (Backward Citations)

US3403341A Cited
US3537011A Cited
US3495175A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1976-09-24 1977-03-26 1977-09-25 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1980-09-24 1981-03-26 1981-09-25 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1984-09-24 1985-03-26 1985-09-25 $7700.00 Window Closed / Lapsed

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