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US3757414A Expired / Lapsed US ⏱️ 0.0 years remaining

Method for batch fabricating semiconductor devices

Assignee: Honeywell Inc
•
Filing: 1971-03-26
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Granted: 1973-09-11
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Expires: 1991-03-26
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Abstract

Abstract A method for batch fabricating semiconductor stress sensors having the semiconductor material diaphragm rigidly joined to a support flange made of the same semiconducting material. Two processed silicon slices, one to form diaphragms and the other to form support flanges, are rigidly joined. The joined slices are then partitioned to form individual stress sensors.

Inventors

  • 👤 H Keller

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-22 19:38
CPC Classifications
H; H10; H10D; H10D48/00; H10D48/50; G; G01; G01L; G01L9/00; G01L9/0041; G01L9/0042; H10P; H10P95/00; H10W; H10W99/00; Y; Y10; Y10T; Y10T29/00; Y10T29/49; Y10T29/49002; Y10T29/49082

Claims Analysis

Total Claims: 19
Claim 1
Independent Claim 58 words
A method for batch fabricating semiconductor material stress sensors comprising: forming diaphragms by recessing at selected locations through a first major surface of a first wafer of said semiconductor material, forming electrical elements in said diaphragms, bonding a second wafer of said semiconductor material to said first wafer, and partitioning said joined wafers to form said stress sensors.
Claim 2
Independent Claim 58 words
A method for batch fabricating semiconductor material stress sensors comprising: forming diaphragms by recessing at selected locations through a first major surface of a first wafer of said semiconductor material, forming electrical elements in said diaphragms, bonding a second wafer of said semiconductor material to said first wafer, and partitioning said joined wafers to form said stress sensors.
Claim 3
Dependent Claim 42 words
The method of claim 1 wherein said bonding is accomplished by: forming access holes through said second wafer located to correspond to said diaphragms in said first wafer, and bonding said wafers together such that said access holes substantially overlap said diaphragms.
Claim 4
Dependent Claim 37 words
The method of claim 1 wherein said bonding is accomplished by: bonding said second wafer to said first wafer, and forming access holes through said second wafer located to correspond to said diaphragms in said first wafer.
Claim 5
Dependent Claim 68 words
The method of claim 1 wherein said forming of diaphragms is accomplished by: masking said first major surface of said first wafer with a first masking material which resists a first selected etching agent, exposing said first major surface at said selected locations, and applying said first etching agent capable of etching said semiconductor material to said masked and exposed first major surface until said recesses are formed.
Claim 6
Dependent Claim 14 words
The method of claim 1 wherein said forming of diaphragms is accomplished by machining.
Claim 7
Dependent Claim 25 words
The method of claim 1 wherein said forming of electrical elements is accomplished through a surface of said diaphragms defining the depth of said recesses.
Claim 8
Dependent Claim 28 words
The method of claim 1 wherein said forming of electrical elements is accomplished through a surface of said diaphragms opposite a surface defining the depth of said recesses.
Claim 9
Dependent Claim 20 words
The method of claim 1 wherein said bonding is accomplished with said second wafer attached to said first major surface.
Claim 10
Dependent Claim 67 words
The method of claim 2 wherein said forming of access holes is accomplished by: masking a second major surface of said second wafer with a masking material which resists a selected etching agent, exposing said second major surface at said corresponding locations, and applying said etching agent capable of etching said semiconductor material to said masked and exposed second major surfaces until said access holes are formed.
Claim 11
Dependent Claim 15 words
The method of claim 2 wherein said forming of access holes is accomplished by machining.
Claim 12
Dependent Claim 30 words
The method of claim 2 wherein said bonding is accomplished with said second wafer attached to a surface of said first wafer on the side opposite said first major surface.
Claim 13
Dependent Claim 45 words
The method of claim 4 wherein said bonding is accomplished by: using as said masking material a material capable of forming an eutectic bond between surfaces of said semiconducting material, and attaching said second wafer to said recessed first major surface by an eutectic bond.
Claim 14
Dependent Claim 120 words
The method of claim 4 wherein said forming of access holes and said bonding is accomplished by: masking said second major surface of said second wafer with a second masking materiAl which resists a second selected etching agent, exposing said second major surface at said corresponding locations, applying said second etching agent capable of etching said semiconductor material to said masked and exposed second major surface until said access holes are formed, using as said first and second selected masking materials those materials capable of forming an eutectic bond between surfaces of said semiconducting material masking with either said first or second selected masking materials, and attaching said second wafer to said recessed first major surface by an eutectic bond.
Claim 15
Dependent Claim 48 words
The method of claim 9 wherein said bonding is accomplished by: using as said masking material a material capable of forming an eutectic bond between surfaces of said semiconducting material, and attaching said first wafer to said second major surface with said access holes by an eutectic bond.
Claim 16
Independent Claim 84 words
A method for batch fabricating semiconductor material stress sensors comprising: forming sets of electrical elements in a first wafer of said semiconductor material at selected locations through a first major surface of said first wafer, forming diaphragms each containing a said set of electrical elements by recessing through a second major surface of said first wafer opposite said first major surface, bonding a second wafer of said semiconductor material to said first major surface, and partitioning said joined wafers to form said stress sensors.
Claim 17
Independent Claim 84 words
A method for batch fabricating semiconductor material stress sensors comprising: forming sets of electrical elements in a first wafer of said semiconductor material at selected locations through a first major surface of said first wafer, forming diaphragms each containing a said set of electrical elements by recessing through a second major surface of said first wafer opposite said first major surface, bonding a second wafer of said semiconductor material to said first major surface, and partitioning said joined wafers to form said stress sensors.
Claim 18
Independent Claim 68 words
A method for batch fabricating semiconductor material stress sensors comprising: forming diaphragms by recessing at selected locations through a first major surface of a first wafer of said semiconductor material, forming electrical elements in said diaphragms, partitioning said first wafer into individual diaphragms, partitioning a second wafer of said semiconductor material into pieces corresponding to said individual diaphragms, and bonding said individual diaphragms and said corresponding pieces together.
Claim 19
Independent Claim 68 words
A method for batch fabricating semiconductor material stress sensors comprising: forming diaphragms by recessing at selected locations through a first major surface of a first wafer of said semiconductor material, forming electrical elements in said diaphragms, partitioning said first wafer into individual diaphragms, partitioning a second wafer of said semiconductor material into pieces corresponding to said individual diaphragms, and bonding said individual diaphragms and said corresponding pieces together.

References Cited (Backward Citations)

US2846626A Cited
US2944321A Cited
US3224069A Cited
US3427708A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1976-09-10 1977-03-12 1977-09-11 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1980-09-10 1981-03-12 1981-09-11 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1984-09-10 1985-03-12 1985-09-11 $7700.00 Window Closed / Lapsed

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