US3757050A
Expired / Lapsed
US
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Thin a definite time position multichannel transmission system using clock pulses each occurring wi
Assignee: Nissan Motor Co Ltd
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Filing: 1971-12-01
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Granted: 1973-09-04
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Expires: 1991-12-01
Abstract
Abstract A multichannel transmission system comprising a generator for supplying to all the transmitters and receivers with a reference signal consisting of a plurality of clock pulse combined with a periodic sequential pulse signal. Each transmitter produces amplitude-modulated carrier pulses each occurring within a time position defined by the clock pulses in accordance with a given information signal to be conveyed. Each receiver opens its gate the same time position as the associated transmitter so as to receive and demodulate the carrier pulses from the transmitter.
Inventors
- 👤 M Mizote
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-22 16:55
CPC Classifications
G; G08; G08C; G08C15/00; G08C15/06; G08C15/12; H; H04; H04J; H04J3/00; H04J3/02; H04J3/06; H04J3/0635; H04J3/0638; H04L; H04L7/00; H04L7/0008; B; B60; B60R; B60R16/00; B60R16/02; B60R16/03; B60R16/0315; H04L7/04; H04L7/06
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
270 words
A time division multichannel transmission system, which comprises: at least one generator for producing a Clock pulse train modulated by an M-sequence signal and for applying said clock pulse train to a reference signal bus line; a plurality of transmitters connected to said reference signal and transmission bus lines and including first delaying means for delaying said M-sequence signal so as to produce a plurality of first delayed replicas of said M-sequence signal which are delayed from one another by the repetition period of said clock pulse train, a first logical circuit means for producing carrier pulses each appearing within a time slot assigned to a distinct signal channel by combining said first delayed replicas, and modulating means for modulating in amplitude said carrier pulses with a given information signal and for sending out the modulated carrier pulses to said transmission line; and a plurality of receivers connected to said reference signal and transmission bus lines and including a second separating means connected to said reference signal bus line for separating said M-sequence signal from said clock pulse train, second delaying means for delaying said M-sequence signal so as to produce a plurality of second delayed replicas of said M-sequence signal which are delayed from one another by the repetition period of said clock pulse train, a second logical circuit means for producing gate pulses each appearing within said time slot by combining said delayed replicas, gate means connected to said transmission line for passing therethrough said carrier pulse during the pulse width of said gate pulse, and demodulating means for demodulating the passed carrier pulse into said information signal.
Claim 2
Dependent Claim
270 words
A time division multichannel transmission system, which comprises: at least one generator for producing a Clock pulse train modulated by an M-sequence signal and for applying said clock pulse train to a reference signal bus line; a plurality of transmitters connected to said reference signal and transmission bus lines and including first delaying means for delaying said M-sequence signal so as to produce a plurality of first delayed replicas of said M-sequence signal which are delayed from one another by the repetition period of said clock pulse train, a first logical circuit means for producing carrier pulses each appearing within a time slot assigned to a distinct signal channel by combining said first delayed replicas, and modulating means for modulating in amplitude said carrier pulses with a given information signal and for sending out the modulated carrier pulses to said transmission line; and a plurality of receivers connected to said reference signal and transmission bus lines and including a second separating means connected to said reference signal bus line for separating said M-sequence signal from said clock pulse train, second delaying means for delaying said M-sequence signal so as to produce a plurality of second delayed replicas of said M-sequence signal which are delayed from one another by the repetition period of said clock pulse train, a second logical circuit means for producing gate pulses each appearing within said time slot by combining said delayed replicas, gate means connected to said transmission line for passing therethrough said carrier pulse during the pulse width of said gate pulse, and demodulating means for demodulating the passed carrier pulse into said information signal.
Claim 3
Dependent Claim
24 words
A time division multichannel transmission system according to claim 1, in which each of said first and second delaying means is a shift register.
Claim 4
Dependent Claim
59 words
A time division multichannel transmission system according to claim 1, in which said demodulator includes an averaging circuit for averaging the carrier pulses passed through said gate means and a discriminating circuit for producing an output when the average of said carrier pulses exceeds a preselected value, whereby said demodulator neglects erroneous decay of one of three carrier pulses.
Claim 5
Dependent Claim
120 words
A time division multichannel transmission system according to claim 1, which further comprises an M-sequence signal checking circuit for checking 3-th order M-sequence signal, said M-sequence signal checking circuit comprises first, second, third and fourth delaying circuits connected in series to one another in the order named and each having a delay time equal to the repetition period of said clock pulse train, a first exclusive OR gate having its inputs connected to said third and fourth delay circuits, a second exclusive OR gate having its input connected to said first delaying circuit and output of said first exclusive OR gate, and timing circuit for producing a signal in accordance with an output signal from said second exclusive OR gate.
Claim 6
Dependent Claim
39 words
A time division multichannel transmission system according to claim 4, in which said timing circuit includs a counter adapted to count the clock pulses and to produce said output signal in accordance with the number of counted clock pulses.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-09-03 | 1977-03-05 | 1977-09-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-09-03 | 1981-03-05 | 1981-09-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-09-03 | 1985-03-05 | 1985-09-04 | $7700.00 | Window Closed / Lapsed |