Trigger circuit for recording and transmitting sampled analog waveforms

Claim 2

An asynchronous trigger circuit comprising: means for controllably sampling an analog signal; means for comparing the sampled value of said signal with the instantaneous value of said signal, said comparing means including means for generating an output signal whenever the instantaneous value of said analog signal changes by a predetermined incremental value with respect to said sampled value of said signal; and means responsive to said output signal for controlling said sampling means to take a new sample of said analog signal.

Claim 3

The trigger circuit in accordance with claim 1 in which said sampling means includes means responsive to a control pulse for triggering the sampling and holding of the instantaneous value of said analog signal; said comparing means includes a first amplifier for generating a first signal of a predetermined polarity whenever the instantaneous value of said analog signal exceeds the sampled value of said analog signal by a first incremental amount; said comparing means includes a second amplifier for generating a second signal of said predetermined polarity whenever the sampled value of said analog signal exceeds the instantaneous value of said analog signal by a second incremental amount; said generating means includes means responsive to either of said first or said second signals for generating a control pulse of a predetermined width; and said controlling means includes means for coupling said control pulse to said triggering means of said sampling means.

Claim 4

An asynchronous trigger circuit comprising: means responsive to a control signal for sampling and holding an analog input signal; means for inverting the sampled value of said input signal; first means for summing said input signal, the inverted sampled value of said input signal, and a first incremental signal of a first polarity to form a first sum signal; second means for summing said input signal, said inverted sampled value of said input signal, and a second incremental signal of a second polarity to form A second sum signal; means for inverting said second sum signal; means responsive to said first and said inverted second sum signals when said sum first signal and said inverted second sum signal are of said second polarity for controlling said sampling and holding means.

Claim 5

An asynchronous trigger circuit comprising: means responsive to a control signal for sampling and holding an analog input signal; means for inverting the sampled value of said input signal; first means for summing said input signal, the inverted sampled value of said input signal, and a first incremental signal of a first polarity to form a first sum signal; second means for summing said input signal, said inverted sampled value of said input signal, and a second incremental signal of a second polarity to form A second sum signal; means for inverting said second sum signal; means responsive to said first and said inverted second sum signals when said sum first signal and said inverted second sum signal are of said second polarity for controlling said sampling and holding means.

Claim 6

The trigger circuit in accordance with claim 3 in which said first summing means includes first, second, and third resistors which are commonly connected to a first current summing point, said input signal being coupled through said first resistor to said first summing point, the inverted sampled value of said input signal being coupled from said inverting means through said second resistor to said first summing point, and said first incremental signal being coupled through said third resistor to said first summing point; and said second summing means includes fourth, fifth, and sixth resistors which are commonly connected to a second current summing point, said input signal being coupled through said fourth resistor to said second summing point, the inverted sampled value of said input signal being coupled from said inverting means through said fifth resistor to said second summing point, and said second incremental signal being coupled through said sixth resistor to said second summing point.

Claim 7

The trigger circuit in accordance with claim 4, said trigger circuit further comprising: a first amplifier having inverting and noninverting inputs and an output where said first sum signal is provided, said first summing point being connected to said noninverting input of said first amplifier and said inverting input of said first amplifier being connected to a point of reference potential.

Claim 8

The trigger circuit in accordance with claim 5 in which said inverting means includes a second amplifier having inverting and noninverting inputs and an output where said second sum signal is provided, said second summing point being connected to said inverting input of said second amplifier and said noninverting input of said second amplifier being connected to said point of reference potential.

Claim 9

The trigger circuit in accordance with claim 6 in which said controlling means includes a logical OR gate which only passes signals of said second polarity; and said controlling means includes a monostable circuit responsive to signals passed by said OR gate for providing a digital pulse of a width sufficient to trigger said sampling and holding means into sampling and holding a new value of said input signal.

Claim 10

The trigger circuit in accordance with claim 7 in which said controlling means includes a relay circuit for coupling said digital pulse to a trigger input of said sampling and holding means, the coil of said relay being included in said monostable circuit and the contacts of said relay being included in said sampling and holding means.

Claim 11

The trigger circuit in accordance with claim 8 in which said OR gate is comprised of a first diode serially connected between the output of said first amplifier and a third current summing point and a second diode serially connected between the output of said second amplifier and said third current summing point.

Claim 12

An asynchronous method for providing a train of binary pulses, the instantaneous duty cycle of which is proportional to the time rate of change of a dynamically varying analog input signal, said method comprising the steps of sampling the instantaneous value of said input signal in response to a control signal; holding the sampled signal; inverting the sampled signal; providing a first sum of the inverted sampled signal, the current instantaneous value of said input signal, and a first incremental signal of a first polarity; providing a second sum of said inverted sampled signal, said current instantaneous value of said input signal, and a second incremental signal of said second polarity; generating a binary control signal if said first sum is a signal of said secOnd polarity or if said second sum is a signal of said first polarity; and utilizing each such control signal for controlling the sampling of a new value of said input signal.

Claim 13

An asynchronous method for providing a train of binary pulses, the instantaneous duty cycle of which is proportional to the time rate of change of a dynamically varying analog input signal, said method comprising the steps of sampling the instantaneous value of said input signal in response to a control signal; holding the sampled signal; inverting the sampled signal; providing a first sum of the inverted sampled signal, the current instantaneous value of said input signal, and a first incremental signal of a first polarity; providing a second sum of said inverted sampled signal, said current instantaneous value of said input signal, and a second incremental signal of said second polarity; generating a binary control signal if said first sum is a signal of said secOnd polarity or if said second sum is a signal of said first polarity; and utilizing each such control signal for controlling the sampling of a new value of said input signal.