US3749896A
Expired / Lapsed
US
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Leading zero suppression display system
Assignee: Sycon Corp
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Filing: 1971-09-24
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Granted: 1973-07-31
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Expires: 1991-09-24
Abstract
Abstract An apparatus for editing information to be presented to a display to remove unwanted leading zeroes. The apparatus includes logic circuit means for accepting information about the digit and the preceding digit and then deciding whether or not to blank the digit. If the blank decision is made the logic circuit provides an inhibit signal. The information provided to the logic includes a signal indicating that the digit be examined is or is not a zero; a signal indicating whether or not the preceding digit was blanked or that this is the first digit; and a signal indicating whether the digit under examination is immediately preceded by a decimal point. The digits examined in an ordered sequence beginning with the highest ordered digit and proceeding toward the lower, each digit being examined in a well-defined time interval and either blanked or not blanked before the next digit is examined.
Inventors
- 👤 I Munt
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 03:22
CPC Classifications
H; H03; H03K; H03K21/00; H03K21/08; G; G06; G06F; G06F3/00; G06F3/14; G06F3/1407; G09; G09G; G09G3/00; G09G3/04
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
191 words
An apparatus for editing a multi-digit character display in ordered sequence to prevent the display of unwanted zeroes comprising the combination of: means for generating a plurality of electrical signals each representative of a digit; first means for examining each said electrical signal and for generating a first output signal when the digit represented by that signal has a zero value; means for generating a second output signal when either the preceding digit was blanked or the digit is the first in the ordered sequence; means for generating a third output signal when the digit under examination is not immediately preceded by the decimal point; and second means for examining said first, second, and third output signals related to each digit in the ordered sequence and for making a display/not display decision for each digit before examining signals related to the next digit in the ordered sequence, said second means for examining comprising logic circuit means for examining said first, second and third output signals for each digit and for producing a signal to inhibit the display of that digit only when said first, second and third output signals exist concurrently.
Claim 2
Independent Claim
191 words
An apparatus for editing a multi-digit character display in ordered sequence to prevent the display of unwanted zeroes comprising the combination of: means for generating a plurality of electrical signals each representative of a digit; first means for examining each said electrical signal and for generating a first output signal when the digit represented by that signal has a zero value; means for generating a second output signal when either the preceding digit was blanked or the digit is the first in the ordered sequence; means for generating a third output signal when the digit under examination is not immediately preceded by the decimal point; and second means for examining said first, second, and third output signals related to each digit in the ordered sequence and for making a display/not display decision for each digit before examining signals related to the next digit in the ordered sequence, said second means for examining comprising logic circuit means for examining said first, second and third output signals for each digit and for producing a signal to inhibit the display of that digit only when said first, second and third output signals exist concurrently.
Claim 3
Dependent Claim
57 words
An apparatus according to claim 1 wherein said second means for examining said first, second and third output signals further includes means for establishing an ordered sequence of time intervals, each of said time intervals being used to examine one of said digits and to sequentially activate the displays in the absence of a signal to inhibit.
Claim 4
Dependent Claim
151 words
An apparatus according to claim 2 wherein said logic circuit means includes a first logic AND gate for producing a blanking signal when said first, second and third output signals are combined; and wherein said means for generating said second output signal includes a bi-stable circuit for storing an input signal during a single time interval and for producing an output signal in the next subsequent time interval only when the digit examined during said single time interval was blanked, said means for generating said second output signal further including a logic OR gate which generates said second output signal when an input signal is obtained from the output of said bi-stable circuit and generates said second output signal when an input signal is received from said means for establishing an ordered sequence of time intervals, which input signal is obtained when the digit being examined is the most significant digit.
Claim 5
Dependent Claim
21 words
An apparatus according to claim 1 wherein said ordered sequence commences with the highest ordered character and proceeds toward the lowest.
Claim 6
Dependent Claim
38 words
An apparatus according to claim 1 wherein said means for generating said second output signal includes a bi-stable circuit settable to a first state when a digit is blanked and a second state when it is not blanked.
Claim 7
Dependent Claim
51 words
An apparatus according to claim 1 wherein said circuit means for generating said third output signal is adjustable to cooperate with a logic format wherein the decimal point is to the left of the digit under examination and wherein the decimal point is to the right of the digit under examination.
Claim 8
Independent Claim
179 words
A method for editing a multi-digit character display in ordered sequence to prevent the display of unwanted zeroes comprising the steps of: generating a plurality of electrical signals each representative of a digit; examining each said electrical signal and generating a first output signAl when the digit represented by that signal has a zero value; generating a second output signal when either the preceding digit was blanked or the digit is the first in the ordered sequence; generating a third output signal when the digit under examination is not immediately adjacent a decimal point; and examining said first, second and third output signals related to each digit in the ordered sequence and making a display / not display decision for each digit before examining signals related to the next digit in the ordered sequence, said examination of the output signals comprising the logic steps of examining said first, second and third output signals for each digit and for producing a signal to inhibit the display of that digit only when said first, second and third output signals exist concurrently.
Claim 9
Independent Claim
179 words
A method for editing a multi-digit character display in ordered sequence to prevent the display of unwanted zeroes comprising the steps of: generating a plurality of electrical signals each representative of a digit; examining each said electrical signal and generating a first output signAl when the digit represented by that signal has a zero value; generating a second output signal when either the preceding digit was blanked or the digit is the first in the ordered sequence; generating a third output signal when the digit under examination is not immediately adjacent a decimal point; and examining said first, second and third output signals related to each digit in the ordered sequence and making a display / not display decision for each digit before examining signals related to the next digit in the ordered sequence, said examination of the output signals comprising the logic steps of examining said first, second and third output signals for each digit and for producing a signal to inhibit the display of that digit only when said first, second and third output signals exist concurrently.
Claim 10
Dependent Claim
54 words
A method according to claim 7 wherein said examining said first, second and third output signals further includes the establishment of an ordered sequence of time intervals, each of said time intervals being used to examine one of said digits and to sequentially activate the display in the absence of a signal to inhibit.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-07-30 | 1977-01-29 | 1977-07-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-07-30 | 1981-01-29 | 1981-07-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-07-30 | 1985-01-29 | 1985-07-31 | $7700.00 | Window Closed / Lapsed |