Toroidal interconnection system

Claim 2

A shift register interconnection system for transferring messages between units of a data processing system, comprising, a plurality of shift registers and means connecting said shift registers into a plurality of rings whereby a message entered at one location on a ring can be shifted in a predetermined direction to the register associated with a destination unit of the same ring, means connecting each unit to receive and transmit messages at corresponding locations on two adjacent rings to form a band of interconnected units, each of said units occupying a segment of a band, and means associated with each unit to transfer a message from one of said rings to another whereby messages can be transferred along appropriate ring and segment lines of the array between a message initiating unit and a destination unit.

Claim 3

A shift register interconnection system for transferring messages between units of a data processing system, comprising, a plurality of shift registers and means connecting said shift registers into a plurality of rings whereby a message entered at one location on a ring can be shifted in a predetermined direction to the register associated with a destination unit of the same ring, said message including a destination segment address field and a bit position signifying whether the message is on an appropriate ring, means connecting each unit to receive and transmit messages at corresponding locations on two adjacent rings to form a band of interconnected units, each of said units occupying a segment of a band, and means associated with each unit and responsive to said bit signifying whether the message is on an appropriate ring to transfer a message from one ring to another of a band to provide an improved path between a message initiating unit and a destination unit and to set said bit to signify that a further such operation is unnecessary.

Claim 4

A shift register interconnection system for transferring messages between units of a data processing system, comprising, a plurality of shift registers and means connecting said shift registers into a plurality of rings whereby a message entered at one location on a ring can be shifted in a predetermined direction to the register associated with a destination unit of the same ring, said message including a destination segment address field and a bit position signifying whether the message is on an appropriate ring, means connecting each unit to receive and transmit messages at corresponding locations on two adjacent rings to form a band of interconnected units, each of said units occupying a segment of a band, and means associated with each unit and responsive to said bit signifying whether the message is on an appropriate ring to transfer a message from one ring to another of a band to provide an improved path between a message initiating unit and a destination unit and to set said bit to signify that a further such operation is unnecessary.

Claim 5

The system of claim 2 including means connecting said units and shift registers in a plurality of bands with rings connecting adjacent bands and arranged to transfer messages between adjacent upper and lower bands and further including means to resolve priority of access to a ring between upper and lower units.

Claim 6

The system of claim 3 including in a message a field defining a segment address and a band address and means for responding to said message address to transfer a message from one ring to another along segments lines of the array.

Claim 7

The system of claim 4 including means connecting said segment lines in closed loops to form an ordered array of units.

Claim 8

The system of claim 5 including means connecting said segment lines to form closed loops whereby the array is analogous to a toroid.

Claim 9

The system of claim 6 wherein said units include input and output buffers for the two adjacent rings and said means for transferring messages along said segment lines includes gates connecting a shift register output to the output buffers associated with the adjacent rings and logic means responsive to the segment address of a message for controlling said gates.

Claim 10

The system of claim 7 including means connecting said gates to transfer a message from a shift register to said output buffers, to said input buffers or to the next register in the ring and said system further includes logic means responsive to address and control bits in a message and to status signals from said buffers for controlling said gates to route a message.

Claim 11

The system of claim 8 wherein said logic means comprises a first logic circuit for the adjacent upper band and a second logic circuit for the adjacent lower band, and each said circuit includes means for comparing the band and segment address of a message with a local band and segment address for routing messages to an adjacent unit.

Claim 12

The system of claim 9 wherein said message includes a bit signifying whether the logic operation is to be performed by a first or a second logic circuit and each said logic circuit further includes means responsive to said message and to the non-coincidence of the message segment and band addresses with the local band and segment address of the associated logic circuit to transfer the message to the output buffer of the adjacent ring of the associated band.