General purpose matrix processor with convolution capabilities

Claim 2

Apparatus for computing a term of a generalized complex convolution of a plurality of vectors having elements comprising complex numeric terms, each element being stored in a memory having at least two matrix storage areas and issuring the values of the coefficients of a complex numeric term encoded in a data signal responsive to a term identification signal specifying the matrix containing the term and the position of the term in the matrix, comprising: a. at least one address parameter storage means; b. term selecting means having an input terminal receiving retrieve signals, for choosing a plurality of terms from each matrix responsive to the contents of the address parameter storage means and transmitting term identification signals to the memory causing issuance of data signals encoding the first and succeeding terms from each chosen plurality of terms responsive respectively to first and succeeding retreive signals; c. computing means having an input terminal receiving the data signals, for transmitting retrieve signals to the term selecting means, computing the complex product of the complex terms encoded in each group of data signals issued responsive to each retrieve signal and forming the complex sum of the complex products; and d. means for varying the contents of the address parameter storage means in a manner dependent on an exteRnal signal.

Claim 3

The apparatus of claim 1 wherein the address parameter storage means further comprises: a. an address register for storing an address number specifying the position of a complex term in its matrix, b. means for setting the address register to the address specifying the first term chosen in the associated matrix response to the external signal, and c. incrementing means for varying the contents of the address register responsive to each retrieve signal.

Claim 4

The apparatus of claim 2 wherein the address register comprises a plurality of binary flip-flops, and wherein said apparatus further comprises means for shifting the contents of the flip-flops a predetermined number of positions.

Claim 5

The apparatus of claim 2 wherein the incrementing means includes storage means for holding an address increment and means for modifying the contents of the address register by the address increment.

Claim 6

The apparatus of claim 4 including means responsive to the external signal for varying the contents of the address increment storage means.

Claim 7

The apparatus of claim 1 including means for storing the sum of the complex products externally to the apparatus.

Claim 8

The apparatus of claim 1 including means for storing the sum of the complex products in the memory.

Claim 9

The apparatus of claim 1 wherein the computing means includes a plurality of multiplier elements concurrently operable for overlapping timewise the computation of products of the complex term coefficients.

Claim 10

Apparatus for computing a generalized complex convolution of a plurality of vectors having elements comprising complex numeric terms, each element being stored in a memory having at least two matrix storage areas and issuing the values of the coefficients of a complex numeric term encoded in a data signal responsive to a term identification signal specifying the matrix containing the term and the position of the term in the matrix comprising: a. at least one address parameter storage means; b. term selecting means having a plurality of input terminals receiving select signals and retrieve signals for choosing, responsive to each select signal and the contents of the address parameter storage means, a plurality of terms from each matrix, and transmitting term identification signals to the memory causing issuance of data signals encoding the first and succeeding terms from each chosen plurality of terms responsive respectively to first and succeeding retrieve signals; c. computing means having a plurality of input terminals receiving select signals and data signals for supplying a plurality of retrieve signals to the term selecting means responsive to each select signal, receiving the group of complex terms issued responsive to each retrieve signal, computing the complex product of the terms so issued, forming the complex sum of the complex products respectively, and storing the coefficients of the complex sum; d. means for varying the contents of the address parameter storage means in a manner dependent on an external signal; and e. control means for transmitting to the term selecting means the computing means at least one select signal.

Claim 11

Apparatus for computing a generalized complex convolution of a plurality of vectors having elements comprising complex numeric terms, each element being stored in a memory having at least two matrix storage areas and issuing the values of the coefficients of a complex numeric term encoded in a data signal responsive to a term identification signal specifying the matrix containing the term and the position of the term in the matrix comprising: a. at least one address parameter storage means; b. term selecting means having a plurality of input terminals receiving select signals and retrieve signals for choosing, responsive to each select signal and the contents of the address parameter storage means, a plurality of terms from each matrix, and transmitting term identification signals to the memory causing issuance of data signals encoding the first and succeeding terms from each chosen plurality of terms responsive respectively to first and succeeding retrieve signals; c. computing means having a plurality of input terminals receiving select signals and data signals for supplying a plurality of retrieve signals to the term selecting means responsive to each select signal, receiving the group of complex terms issued responsive to each retrieve signal, computing the complex product of the terms so issued, forming the complex sum of the complex products respectively, and storing the coefficients of the complex sum; d. means for varying the contents of the address parameter storage means in a manner dependent on an external signal; and e. control means for transmitting to the term selecting means the computing means at least one select signal.

Claim 12

The apparatus of claim 9 wherein the address parameter storage means further comprises: a. a start address register; b. means for setting the start address register to a number specifying the matrix position of the first complex numeric term chosen responsive to the first select signal, and c. incrementing means for varying the contents of the start address register responsive to each select signal.

Claim 13

The apparatus of claim 9 wherein the control means includes means for causing the computing of a plurality of complex numeric values Sj, each Sj comprising the sum of the first through j th complex sums computed; and means for causing the control means to issue first through j th select signals.

Claim 14

The apparatus of claim 9 wherein the address parameter sTorage means further comprises: a. a current address register containing an integer specifying the position of a term in a matrix and issuing a term identification signal for that term responsive to a retrieve signal; b. a current address increment storage means containing an integer, for specifying the number of complex terms between successive complex terms chosen from the matrix; and c. incrementing means receiving retrieve signals for increasing the integer contained in the current address register by the integer contained in the current address increment storage means responsive to a retrieve signal.

Claim 15

The apparatus of claim 9 wherein the control means includes testing means for testing the sign of a previously computed sum and changing the contents of the address parameter storage means dependent on the sign.

Claim 16

Apparatus for computing a generalized real convolution of a plurality of vectors having elements comprising real numeric terms, the value of each element being stored in a memory having at least two matrix storage areas and issuing a data signal in which is encoded the value of a real term responsive to a term identification signal specifying the matrix containing the term and the position of the term in the matrix, comprising: a. integer storage means for storing the values of first and second preselected integers for each matrix and a variable integer for each matrix; b. term selecting means receiving retrieve and select signals for incrementing the variable integers for each matrix by the value of the first preselected integer for that matrix responsive to a retrieve signal, incrementing the variable integer for each matrix by the value of the second preselected integer for that matrix responsive to a select signal and emitting, responsive to a retrieve signal, term identification signals specifying the term in each matrix occupying the position specified by its respective variable integer; c. computing means having an input terminal receiving the data signals and select signals for transmitting a plurality of retrieve signals to the term selecting means responsive to each select signal, computing the products of the terms encoded in data signals issued by the memory after each retrieve signal and forming the sum of the products formed from the data signals issued responsive to each select signal; and d. control means for transmitting to the term selecting means and the computing means at least one select signal.

Claim 17

Apparatus for computing a generalized real convolution of a plurality of vectors having elements comprising real numeric terms, the value of each element being stored in a memory having at least two matrix storage areas and issuing a data signal in which is encoded the value of a real term responsive to a term identification signal specifying the matrix containing the term and the position of the term in the matrix, comprising: a. integer storage means for storing the values of first and second preselected integers for each matrix and a variable integer for each matrix; b. term selecting means receiving retrieve and select signals for incrementing the variable integers for each matrix by the value of the first preselected integer for that matrix responsive to a retrieve signal, incrementing the variable integer for each matrix by the value of the second preselected integer for that matrix responsive to a select signal and emitting, responsive to a retrieve signal, term identification signals specifying the term in each matrix occupying the position specified by its respective variable integer; c. computing means having an input terminal receiving the data signals and select signals for transmitting a plurality of retrieve signals to the term selecting means responsive to each select signal, computing the products of the terms encoded in data signals issued by the memory after each retrieve signal and forming the sum of the products formed from the data signals issued responsive to each select signal; and d. control means for transmitting to the term selecting means and the computing means at least one select signal.

Claim 18

The apparatus of claim 14 wherein the control means includes presetting means for presetting the variable integers prior to emission of the first select signal.

Claim 19

The apparatus of claim 14 wherein the control means includes testing means for testing the sign of a previously computed sum and changing the contents of the integer storage means in a manner dependent on the sign.

Claim 20

Apparatus for computing a generalized complex convolution of a plurality of vectors having elements comprising complex numeric terms, each element being stored in a memory having at least two matrix storage areas and issuing the value of a complex term encoded in a data signal responsive to a term identification signal specifying the matrix containing the term and the position of the term in the matrix, comprising: a. integer storage means for storing the values of first and second preselected integers for each matrix and a variable integer for each matrix; b. term selecting means receiving retrieve and select signals, for incrementing the variable integer for each matrix by the value of the first preselected integer for each matrix responsive to a retrieve signal, incrementing the variable integer for each matrix by the value of the second preselected integer for that matrix responsive to a select signal and issuing responsive to a retrieve signal, term identification signals specifying the term in each matrix occupying the position specified by its respective variable integer; c. computing means haviNg an input terminal receiving the data signals and select signals, for transmitting a plurality of retrieve signals to the term selecting means responsive to each select signal, computing the product of the terms encoded in data signals emitted by the memory after each retrieve signal, and forming the complex sum of the products formed from the data signals emitted responsive to each select signal; and d. control means for transmitting to the term selecting means and the computing means at least one select signal.

Claim 21

Apparatus for computing a generalized complex convolution of a plurality of vectors having elements comprising complex numeric terms, each element being stored in a memory having at least two matrix storage areas and issuing the value of a complex term encoded in a data signal responsive to a term identification signal specifying the matrix containing the term and the position of the term in the matrix, comprising: a. integer storage means for storing the values of first and second preselected integers for each matrix and a variable integer for each matrix; b. term selecting means receiving retrieve and select signals, for incrementing the variable integer for each matrix by the value of the first preselected integer for each matrix responsive to a retrieve signal, incrementing the variable integer for each matrix by the value of the second preselected integer for that matrix responsive to a select signal and issuing responsive to a retrieve signal, term identification signals specifying the term in each matrix occupying the position specified by its respective variable integer; c. computing means haviNg an input terminal receiving the data signals and select signals, for transmitting a plurality of retrieve signals to the term selecting means responsive to each select signal, computing the product of the terms encoded in data signals emitted by the memory after each retrieve signal, and forming the complex sum of the products formed from the data signals emitted responsive to each select signal; and d. control means for transmitting to the term selecting means and the computing means at least one select signal.

Claim 22

The apparatus of claim 17 wherein the control means includes presetting means for presetting the variable integers prior to emission of the first select signal.

Claim 23

Apparatus for computing an equation comprising: a. control signal means for supplying data address control signals encoding preselected integers k, P, Q, U, and V, and a preselected loop count signal LC; b. data signal means for encoding first and second ordered pluralities of data signals Ao through Am and Bo through Bn wherein each A and B comprises a complex number of the form x + y Square Root -1; c. memory means receiving the signals supplied by the control signal means and the data signal means, for storing each signal and supplying each signal responsive to a retrieve signal designating the stored signal; and d. an arithmetic unit sequentially supplying a plurality of retrieve signals to the memory means and providing responsive to the retrieved signals from the memory means, an output signal encoding a complex number Ck of the form x + y Square Root -1 computed according to the equation

Claim 24

Apparatus for computing an equation comprising: a. control signal means for supplying data address control signals encoding preselected integers k, P, Q, U, and V, and a preselected loop count signal LC; b. data signal means for encoding first and second ordered pluralities of data signals Ao through Am and Bo through Bn wherein each A and B comprises a complex number of the form x + y Square Root -1; c. memory means receiving the signals supplied by the control signal means and the data signal means, for storing each signal and supplying each signal responsive to a retrieve signal designating the stored signal; and d. an arithmetic unit sequentially supplying a plurality of retrieve signals to the memory means and providing responsive to the retrieved signals from the memory means, an output signal encoding a complex number Ck of the form x + y Square Root -1 computed according to the equation

Claim 25

Apparatus for computing equation comprising: a. control signal means for supplying data address control signals encoding preselected integers k, P, Q, U, and V, and a preselected loop count signal LC; b. data signal means for encoding first and second ordered pluralities of data signals ao through am and bo through bn wherein each a and b comprises a real number; c. memory means receiving the signals supplied by the control signal means and the data signal means, for storing each signal and supplying each signal responsive to a retrieve signal designating the stored signal; and d. an arithmetic unit sequentially supplying a plurality of retrieve signals to the memory means and providing responsive to the retrieved signals from the memory means, an output signal encoding a real number Ck computed according to the equation:

Claim 26

Apparatus for computing equation comprising: a. control signal means for supplying data address control signals encoding preselected integers k, P, Q, U, and V, and a preselected loop count signal LC; b. data signal means for encoding first and second ordered pluralities of data signals ao through am and bo through bn wherein each a and b comprises a real number; c. memory means receiving the signals supplied by the control signal means and the data signal means, for storing each signal and supplying each signal responsive to a retrieve signal designating the stored signal; and d. an arithmetic unit sequentially supplying a plurality of retrieve signals to the memory means and providing responsive to the retrieved signals from the memory means, an output signal encoding a real number Ck computed according to the equation:

Claim 27

Apparatus for computing an equation comprising: a. control signal means for supplying data address control signals encoding preselected integers k, P, Q, U, and V, and a preselected loop count signal LC; b. data signal means for encoding first and second ordered pluralities of data signals ao through am and bo through bn wherein each a and b comprises a real number; c. memory means receiving the signals supplied by the control signal means and the data signal means, for storing each signal and supplying each signal responsive to a retrieve signal designating the stored signal; and d. an arithmetic unit sequentially supplying a plurality of retrieve signals to the memory means and providing responsive to the retrieved signals from the memory means, an output signal encoding a real number Ck computed according to the equation:

Claim 28

Apparatus for computing an equation comprising: a. control signal means for supplying data address control signals encoding preselected integers k, P, Q, U, and V, and a preselected loop count signal LC; b. data signal means for encoding first and second ordered pluralities of data signals ao through am and bo through bn wherein each a and b comprises a real number; c. memory means receiving the signals supplied by the control signal means and the data signal means, for storing each signal and supplying each signal responsive to a retrieve signal designating the stored signal; and d. an arithmetic unit sequentially supplying a plurality of retrieve signals to the memory means and providing responsive to the retrieved signals from the memory means, an output signal encoding a real number Ck computed according to the equation: