US3740538A
Expired / Lapsed
US
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Digital sorter and ranker
Assignee: United States Department of the Air Force
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Filing: 1971-07-28
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Granted: 1973-06-19
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Expires: 1991-07-28
Abstract
Abstract A digital sorter and ranker in which pairs of binary words are subtracted from each other in adders by feed-in in one word of the pair together with the adjacent word one''s complement. A carry output indicates which word is the lowest and this output is fed through coincidence logic circuits to additional series of address and logic circuits in pyramid fashion until a single output is obtained from a final adder. The adder logic circuits, the carry output and the output of the final adder are fed through minimum value logic circuits to a series of minimum value flip-flops with the outputs thereof being fed back to the adders and their logic circuits. To record the rank of each word, a series of flip-flop groups with each group corresponding to a binary word is set according to the word''s rank, the flip-flops being controlled by gating circuits fed by preceding logic circuits, the final adder, and a binary counter.
Inventors
- 👤 J Hemphill
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 07:48
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/22; G06F7/24; G06F2207/00; G06F2207/22; G06F2207/222; G06F2207/226
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
291 words
A system for sorting and ranking a series of binary words comprising: a. a first series of comparing adders, each adder fed by a sequential pair of words from the series of binary words with one of each pair being a one''s complement and having an output representing the lowest value thereof; b. a first series of pairs of coincidence logic circuits, each pair corresponding to one each of the first series of comparing adders fed by the output of the comparing adder; c. a second series of coincidence logic circuits fed by one pair each of the first series of pairs of conicidence logic circuits and by the corresponding pais of binary words; d. a second series of comparinG adders, each adder fed by pairs of the second series of coincidence logic circuits; e. a third series of pairs of coincidence logic circuits each pair enabled by one of the second series of comparing adders; f. a fourth series of coincidence logic circuits fed by one each of the third series of coincidence logic circuits and sequential pairs of the second series of coincidence logic circuits; g. a final comparing adder fed by the fourth series of coincidence logic circuits; h. a series of minimum value gating circuits fed by the final comparing adder, the first series of pairs of coincidence logic circuits, and the third series of pairs of coincidence logic circuits; i. a counter feeding the series of minimum value gating circuits; and j. a series of minimum value flip-flops each corresponding to one binary word and fed by one each of the series of minimum value gating circuits, the output of the minimum value flipflops being fed to the first and third series of coincidence logic circuits.
Claim 2
Independent Claim
291 words
A system for sorting and ranking a series of binary words comprising: a. a first series of comparing adders, each adder fed by a sequential pair of words from the series of binary words with one of each pair being a one''s complement and having an output representing the lowest value thereof; b. a first series of pairs of coincidence logic circuits, each pair corresponding to one each of the first series of comparing adders fed by the output of the comparing adder; c. a second series of coincidence logic circuits fed by one pair each of the first series of pairs of conicidence logic circuits and by the corresponding pais of binary words; d. a second series of comparinG adders, each adder fed by pairs of the second series of coincidence logic circuits; e. a third series of pairs of coincidence logic circuits each pair enabled by one of the second series of comparing adders; f. a fourth series of coincidence logic circuits fed by one each of the third series of coincidence logic circuits and sequential pairs of the second series of coincidence logic circuits; g. a final comparing adder fed by the fourth series of coincidence logic circuits; h. a series of minimum value gating circuits fed by the final comparing adder, the first series of pairs of coincidence logic circuits, and the third series of pairs of coincidence logic circuits; i. a counter feeding the series of minimum value gating circuits; and j. a series of minimum value flip-flops each corresponding to one binary word and fed by one each of the series of minimum value gating circuits, the output of the minimum value flipflops being fed to the first and third series of coincidence logic circuits.
Claim 3
Dependent Claim
68 words
A system for sorting and ranking a series of binary words according to claim 1 which further comprises: a. a plurality of series of ranking flip-flops, each series corresponding to a binary word; b. a plurality of ranking gating circuits interposed between the ranking flip-flop and the minimum value gating coincidence logic circuits, and c. a binary counter feeding enabling pulses to the plurality of ranking gating circuits.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-06-18 | 1976-12-18 | 1977-06-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-06-18 | 1980-12-18 | 1981-06-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-06-18 | 1984-12-18 | 1985-06-19 | $7700.00 | Window Closed / Lapsed |