Patent US6379319B1 successfully refreshed from Google Patents.
US3739237A
Expired / Lapsed
US
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Methods of manufacturing insulated gate field effect transistors
Assignee: US Philips Corp
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Filing: 1970-12-18
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Granted: 1973-06-12
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Expires: 1990-12-18
Abstract
Abstract A method of making an IGFET by implantation techniques is described. The method features provision of the source and drain contact metal on the semiconductor surface and an adjoining insulator, provision of a gate electrode structure which will mask ions, and then ion bombardment under such conditions that the ions do not penetrate the gate electrode structure thereby defining a channel precisely aligned with the gate, but ions do penetrate the adjacent structure to form in the underlying semiconductor source and drain surface regions wholly defined by the implantation and whose p-n junctions terminate under the insulator. Upon completion, the source and drain contacts for the source and drain regions are automatically established. Various methods are described for controlling the locations where the ions are masked or are permitted to penetrate into the semiconductor.
Inventors
- 👤 J Shannon
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-22 21:03
CPC Classifications
H; H10; H10D; H10D99/00; H10D30/00; H10D30/60; Y; Y10; Y10S; Y10S148/00; Y10S148/02; Y10S148/053
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
257 words
A method of manufacturing an insulated gate field effect transistor having spaced source and drain regions whose edges terminate at a surface of a semiconductor body and which are separated by a surface channel region, comprising providing a semiconductor body having a surface portion of one conductivity type, providing on the surface portion a layer of ion-penetrating insulating material, providing over only the channel region to be formed an ion-masking gate electrode structure, providing over body portions bounding the source and drain edges to be formed and remote from the channel an ion-masking layer, forming in the ion-penetrating insulating layer openings located over and smaller than the source and drain regions to be formed and lying inside of and spaced from said source drain peripheral edges, providing source and drain electrode layers comprising ionpenetrating continuous metal layers extending over the insulating material and through the said openings to form ohmic contacts with the source and drain regions to be formed, and thereafter ion bombarding said surface with ions of a conductivity type determining impurity element characteristic of the opposite conductivity type under conditions such that the ions do not penetrate the ion-masking layers but do penetrate the ionpenetratinG layers to thereby form in the surface portion wholly by ion implantation source and drain regions of the opposite conductivity type forming p-n junction edges which terminate at the surface below said insulating material and which define below the gate electrode layer a channel region whose length is substantially equal to the corresponding dimension of the gate electrode layer.
Claim 2
Independent Claim
257 words
A method of manufacturing an insulated gate field effect transistor having spaced source and drain regions whose edges terminate at a surface of a semiconductor body and which are separated by a surface channel region, comprising providing a semiconductor body having a surface portion of one conductivity type, providing on the surface portion a layer of ion-penetrating insulating material, providing over only the channel region to be formed an ion-masking gate electrode structure, providing over body portions bounding the source and drain edges to be formed and remote from the channel an ion-masking layer, forming in the ion-penetrating insulating layer openings located over and smaller than the source and drain regions to be formed and lying inside of and spaced from said source drain peripheral edges, providing source and drain electrode layers comprising ionpenetrating continuous metal layers extending over the insulating material and through the said openings to form ohmic contacts with the source and drain regions to be formed, and thereafter ion bombarding said surface with ions of a conductivity type determining impurity element characteristic of the opposite conductivity type under conditions such that the ions do not penetrate the ion-masking layers but do penetrate the ionpenetratinG layers to thereby form in the surface portion wholly by ion implantation source and drain regions of the opposite conductivity type forming p-n junction edges which terminate at the surface below said insulating material and which define below the gate electrode layer a channel region whose length is substantially equal to the corresponding dimension of the gate electrode layer.
Claim 3
Dependent Claim
13 words
An insulated gate field effect transistor made by the process of claim 1.
Claim 4
Dependent Claim
27 words
A method as claimed in claim 1 wherein a gate electrode is provided which has a different structure compared to the source and drain metal layer parts.
Claim 5
Dependent Claim
29 words
A method as claimed in claim 3, wherein the gate electrode is of metal and is of different composition than that of the source and drain metal layer parts.
Claim 6
Dependent Claim
32 words
A method as claimed in claim 4, wherein the source and drain metal layer parts are of aluminum and the gate electrode comprises a molybdenum or nickel layer on the insulating material.
Claim 7
Dependent Claim
36 words
A method as claimed in claim 5, wherein the gate electrode further comprises an aluminum layer on the molybdenum or nickel layer, said aluminum layer being provided simultaneously with the source and drain metal layer parts.
Claim 8
Dependent Claim
37 words
A method as claimed in claim 3, wherein the gate electrode is of metal and the source and drain metal layer parts are of the same metal but of smaller thickness than the gate electrode metal layer.
Claim 9
Dependent Claim
57 words
A method as claimed in claim 3, wherein the insulating material is on the surface below a gate electrode layer and the insulating material on the surface below the source and drain metal layer parts adjacent the openings consist of the same insulating layer which is formed prior to providing the source, drain and gate electrode layers.
Claim 10
Dependent Claim
73 words
A method as claimed in claim 8, wherein a first, thicker insulating layer is provided on the semiconductor surface, an area of said first insulating layer is removed, and therafter a second, thinner ion-penetrating insulating layer is formed on the semiconductor surface at said area, openings being formed in the thinner insulating layer and the gate electrode layer and the source and drain metal layer parts being provided on the thinner insulating layer.
Claim 11
Dependent Claim
56 words
A method as claimed in claim 9, wherein the source, drain and gate electrode layers further extend on the first thicker insulating layer, the parts of the electrode layers on the first thicker insulating layer having a thickness sufficient to prevent the penetration of the bombarding ions into the underlying thicker insulating layer and semiconductor surface.
Claim 12
Dependent Claim
56 words
A method as claimed in claim 1, wherein the source and drain metal layer parts are provided so that they do not occupy the total area of the openings in the insulating material, and implantation of ions is effected preferentially in the surface parts below the openings which are not covered by the metal layer parts.
Claim 13
Dependent Claim
54 words
A method as claimed in claim 1, wherein the conditions of ion bombardment are such that at least at the areas where the source and drain metal layer parts contact the semiconductor surface atoms of the metal layer parts are caused to enter the underlying surface parts by energy transfer from the bombarding ions.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-06-11 | 1976-12-11 | 1977-06-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-06-11 | 1980-12-11 | 1981-06-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-06-11 | 1984-12-11 | 1985-06-12 | $7700.00 | Window Closed / Lapsed |