Patent JPS57115518A successfully refreshed from Google Patents.
US3739160A
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Method and apparatus for fault testing binary circuit subsystems
Assignee: Unisys Corp
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Filing: 1971-11-08
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Granted: 1973-06-12
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Expires: 1991-11-08
Abstract
Abstract A subsystem of binary circuits, packaged in modular form and having a plurality of connection points through which it is incorporated into a master system such as a digital computer, is tested by utilizing a binary word generator that periodically generates a string of parallel binary bits for application to the subsystem under test. Output signals from the subsystem under test are continually monitored and supplied to the binary word generator to shape the character of the succeeding string of parallel binary bits (binary word) applied to the subsystem. If there are no faults in the subsystem under test, starting the word generator and the digital circuits in the subsystem from respective initial reference states, insures that the binary word applied to the subsystem by the word generator, after a certain number of word applications or periods, will always be the same, for the same initial states and number of periods. A different binary word, than the one expected for a subsystem having no faults, is generated at the end of a test cycle when an identically structured subsystem having a fault or faults therein is tested under the same initial conditions and number of periods. To isolate the fault-containing portion of a subsystem when the expected word is not generated, the output connection points of the subsystem are disconnected from the input connection points of the binary word generator, the binary circuit subsystem and word generator are placed into an initial or reference state, and the binary signals appearing at each output connection point of the subsystem are counted during a cycle of word applications by the word generator. The count of binary signals generated at each output connection point of the binary subsystem will always be the same number for the same number of word applications and the same set of initial states for the binary word generator and the subsystem, if there are no faults in the subsystem. If there is a fault in a circuit connected to a particular output connection point of the subsystem, the count of binary signals appearing at this point for one test cycle, (a particular number of word applications) will be different than expected, while the count at all the other output connection points will be the same as expected, assuming that the initial states of the binary word generator and the binary subsystem, and the number of word applications remained the same.
Inventors
- 👤 Hasan H El
- 👤 R Packard
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 12:07
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/319; G01R31/31917; G06; G06F; G06F11/00; G06F11/22; G06F11/26; G06F11/273; G06F11/277; G06F7/00; G06F7/58; G06F7/582; G06F11/07; G06F11/0703; G06F11/0751; G06F11/0754; G06F11/076
Claims Analysis
Total Claims: 46
Claim 1
Independent Claim
72 words
In an apparatus for fault-testing a binary circuit subsystem having a plurality of input and output connection points, a binary signal generator for periodically applying a pattern of binary signals to said subsystem comprising: means for generating binary signals in a pattern caused by binary signals received from the output connection points of said subsystem; and means for supplying said generated binary signal pattern to the input connection points of said subsystem.
Claim 2
Dependent Claim
72 words
In an apparatus for fault-testing a binary circuit subsystem having a plurality of input and output connection points, a binary signal generator for periodically applying a pattern of binary signals to said subsystem comprising: means for generating binary signals in a pattern caused by binary signals received from the output connection points of said subsystem; and means for supplying said generated binary signal pattern to the input connection points of said subsystem.
Claim 3
Dependent Claim
74 words
The binary signal generator of claim 1 wherein said binary signal generating means comprises: a plurality of logic elements receiving biNary input signals from the output connection points of said subsystem and generating binary output signals in response to the received signals; and a plurality of bistable elements responsive to the binary signals generated by said logic elements for generating binary output signals to be applied to the input connection points of said subsystem.
Claim 4
Dependent Claim
41 words
The binary signal generator of claim 2 wherein said plurality of bistable elements are connected serially in a closed loop with said plurality of logic elements, one of said plurality of logic elements being connected between a pair of bistable elements.
Claim 5
Dependent Claim
74 words
The signal generator of claim 3 wherein each one of said plurality of logic elements has three input terminals and one output terminal, the first input terminal receiving binary signals from an immediately preceding bistable element, the second input terminal receiving binary signals from the subsystem under test, the third input terminal receiving binary signals from the immediately subsequent bistable element, and the output terminal supplying binary signals to said immediately subsequent bistable element.
Claim 6
Dependent Claim
61 words
The signal generator of claim 3 wherein each one of said plurality of logic elements has two input terminals and one output terminal, the first input terminal receiving binary signals from an immediately preceding bistable element, the second input terminal receiving binary signals from the subsystem under test, and the output terminal supplying binary signals to the immediately subsequent bistable element.
Claim 7
Dependent Claim
45 words
The binary signal generator of claim 2 wherein said plurality of logic elements equal in number said plurality of bistable elements and said plurality of logic or bistable elements are less in number than the plurality of input and output connection points on said subsystem.
Claim 8
Dependent Claim
41 words
The binary signal generator of claim 6 wherein said plurality of bistable elements are connected serially in a closed loop with said plurality of logic elements, one of said plurality of logic elements being connected between a pair of bistable elements.
Claim 9
Dependent Claim
82 words
The signal generator of claim 7 wherein each one of said plurality of logic elements has three input terminals and one output terminal, the first input terminal receiving binary signals from an immediately preceding bistable element, the second input terminal receiving binary signals from the subsystem under test when paired with a subsystem output connection point, the third input terminal receiving binary signals from the immediately subsequent bistable element, and the output terminal supplying binary signals to said immediately subsequent bistable element.
Claim 10
Dependent Claim
69 words
The signal generator of claim 7 wherein each one of said plurality of logic elements has two input terminals and one output terminal, the first input terminal receiving binary signals from an immediately preceding bistable element, the second input terminal receiving binary signals from the subsystem under test when paired with a subsystem output connection point, and the output terminal supplying binary signals to the immediately subsequent bistable element.
Claim 11
Dependent Claim
123 words
In an apparatus for fault-testing a binary circuit subsystem having a plurality of input and output connection points, a binary signal generator for periodically applying a plurality of binary signals to said subsystem, comprising: a plurality of logic elements responsive to binary signals at the output connection points of said subsystem, each of said logic elements receiving more than one binary input signal and generating a binary output signal only when a certain combination of input signals is received; and a plurality of bistable elements, responsive to the binary signals generated by said logic elements, each of said bistable elements changing state in response to binary input signals for generating binary signals to be applied to the input connection points of said subsystem.
Claim 12
Dependent Claim
123 words
In an apparatus for fault-testing a binary circuit subsystem having a plurality of input and output connection points, a binary signal generator for periodically applying a plurality of binary signals to said subsystem, comprising: a plurality of logic elements responsive to binary signals at the output connection points of said subsystem, each of said logic elements receiving more than one binary input signal and generating a binary output signal only when a certain combination of input signals is received; and a plurality of bistable elements, responsive to the binary signals generated by said logic elements, each of said bistable elements changing state in response to binary input signals for generating binary signals to be applied to the input connection points of said subsystem.
Claim 13
Dependent Claim
41 words
The signal generator of claim 10 wherein said plurality of bistable elements are connected sErially in a closed loop with said plurality of logic elements, one of said plurality of logic elemenets being connected between a pair of said bistable elements.
Claim 14
Dependent Claim
74 words
The signal generator of claim 10 wherein each one of said plurality of logic elements has three input terminals and one output terminal, the first input terminal receiving binary signals from an immediately preceding bistable element, the second input terminal receiving binary signals from the subsystem under test, the third input terminal receiving binary signals from the immediately subsequent bistable element, and the output terminal supplying binary signals to said immediately subsequent bistable element.
Claim 15
Dependent Claim
61 words
The signal generator of claim 11 wherein each one of said plurality of logic elements has two input terminals and one output terminal, the first input terminal receiving binary signals from an immediately preceding bistable element, the second input terminal receiving binary signals from the subsystem under test, and the output terminal supplying binary signals to the immediately subsequent bistable element.
Claim 16
Independent Claim
93 words
An apparatus for fault-testing a binary circuit subsystem having a plurality of input and output connection points, comprising: means for generating binary signals to be applied to said subsystem in patterns caused by binary signals received from the output connection points of said subsystem; and means for initializing said binary circuit subsystem and said binary signal generating means, whereby the binary signals generated and applied to said subsystem thereafter, for N periods, are a characteristic combination of binary signals for each value of N when there are no faults in said binary circuit.
Claim 17
Independent Claim
93 words
An apparatus for fault-testing a binary circuit subsystem having a plurality of input and output connection points, comprising: means for generating binary signals to be applied to said subsystem in patterns caused by binary signals received from the output connection points of said subsystem; and means for initializing said binary circuit subsystem and said binary signal generating means, whereby the binary signals generated and applied to said subsystem thereafter, for N periods, are a characteristic combination of binary signals for each value of N when there are no faults in said binary circuit.
Claim 18
Dependent Claim
41 words
The apparatus of claim 14 further comprising: means for displaying the binary signals generated during the Nth period, thereby permitting an observation to be made as to whether a characteristic combination or a non-characteristic combination of binary signals has been generated.
Claim 19
Dependent Claim
25 words
The apparatus of claim 14 further comprising: switching means, for connecting and disconnecting signal paths between said binary subsystem and said binary signal generating means.
Claim 20
Dependent Claim
45 words
The apparatus of claim 16 further comprising: means for selectively deactivating said switching means; means for sensing the number of binary signals present in the signal paths having deactivated switching means; and means for displaying the number of binary signals sensed by said sensing means.
Claim 21
Dependent Claim
63 words
The apparatus of claim 14 wherein said means for periodically generating a plurality of binary signals comprises: first means responsive to binary signals at the output connection points of said subsystem, for generating binary signals; and second means responsive to the binary signals generated by said first means for generating binary signals to be applied to the input connection points of said subsystem.
Claim 22
Dependent Claim
67 words
The apparatus of claim 18 wherein said second means is a plurality of bistable elements, each of said bistable elements changing state in response to binary input signals; and wherein said first means is a plurality of logic elements, each of said logic elements receiving more than one binary input signal and generating a binary output signal only when a certain combination of input signals is received.
Claim 23
Dependent Claim
40 words
The apparatus of claim 19 wherein said plurality of bistable elements are connected serially in a closed loop with said plurality of logic elements, one of said plurality of logic elements being connected between a pair of said bistable elements.
Claim 24
Dependent Claim
70 words
The apparatus of claim 20 wherein each one of said plurality of logic elements has three input terminals and one output terminal, the first input terminal receiving digital signals from an immediately preceding bistable element, the second input terminal receiving signals from said subsystem under test, the third input terminal receiving signals from an immediately subsequent bistable element, and the output termiNal supplying signals to said immediately subsequent bistable element.
Claim 25
Dependent Claim
22 words
The apparatus of claim 21 further comprising: means for supplying the binary signals from said bistable elements to said binary circuit subsystem.
Claim 26
Dependent Claim
25 words
Tje apparatus of claim 22 further comprising: switching means for connecting and disconnecting signal paths between said binary subsystem and said binary signal generating means.
Claim 27
Dependent Claim
45 words
The apparatus of claim 23 further comprising: means for selectively deactivating said switching means; means for sensing the number of binary signals present in the signal paths having deactivated switching means; and means for displaying the number of binary signals sensed by said sensing means.
Claim 28
Dependent Claim
59 words
The apparatus of claim 20 wherein each one of said plurality of logic elements has two input terminals and one output terminal, the first input terminal receiving digital signals from an immediately preceding bistable element, the second input terminal receiving digital signals from said subsystem under test, and the output terminal supplying signals to an immediately subsequent bistable element.
Claim 29
Dependent Claim
22 words
The apparatus of claim 25 further comprising: means for supplying the binary signals from said bistable elements to said binary circuit subsystem.
Claim 30
Dependent Claim
25 words
The apparatus of claim 26 further comprising: switching means, for connecting and disconnecting signal paths between said binary subsystem and said binary signal generating means.
Claim 31
Dependent Claim
45 words
The apparatus of claim 27 further comprising: means for selectively deactivating said switching means; means for sensing the number of binary signals present in the signals paths having deactivated switching means; and means for displaying the number of binary signals sensed by said sensing means.
Claim 32
Dependent Claim
35 words
The apparatus of claim 20 wherein said plurality of bistable elements equal in number said plurality of logic elements and are greater in number than the plurality of connection points on said subsystem under test.
Claim 33
Dependent Claim
38 words
The apparatus of claim 29 further comprising: a plurality of switching means, one switching means for each one of said plurality of bistable or logic elements for connecting said binary circuit subsystem and said binary word generator together.
Claim 34
Dependent Claim
76 words
The apparatus of claim 30 wherein each one of said plurality of logic elements has three input terminals and one output terminal, the first input terminal connected to an output of an immediately preceding bistable element, the second input terminal connected to one of said plurality of switching means, the third input terminal connected to an output of an immediately subsequent bistable element, and the output terminal conected to an input of said subsequuent bistable element.
Claim 35
Dependent Claim
26 words
The apparatus of claim 31 wherein each one of the outputs of said bistable elements is also connected to one of said plurality of switching means.
Claim 36
Dependent Claim
45 words
The apparatus of claim 32 further comprising: means for selectively deactivating said switching means; means for sensing the number of binary signals generated at the signal paths having deactivated switching means; and means for displaying the number of binary signals sensed by said sensing means.
Claim 37
Dependent Claim
63 words
The apparatus of claim 30 wherein each one of said plurality of logic elements has two input terminals and one output terminal, the first input terminal connected to an output of an immediately preceding bistable element, the second input terminal connected to one of said plurality of switching means, and the output terminal connected to an input of an immediately subsequent bistable element.
Claim 38
Dependent Claim
26 words
The apparatus of claim 34 wherein each one of the outputs of said bistable elements is also connected to one of said plurality of switching means.
Claim 39
Dependent Claim
45 words
The apparatus of claim 35 further comprising: means for selectively deactivating said switching means; means for sensing the number of binary signals generated at the connection points having deactivated switching means; and means for diSplaying the number of binary signals sensed by said sensing means.
Claim 40
Independent Claim
54 words
A method of fault-testing a binary circuit subsystem having a plurality of input and output connection points comprising: setting said subsystem to a reference state; and starting from a reference state, generating and applying binary signals to said subsystem in patterns caused by binary signals received from the output connection points of said subsystem.
Claim 41
Independent Claim
54 words
A method of fault-testing a binary circuit subsystem having a plurality of input and output connection points comprising: setting said subsystem to a reference state; and starting from a reference state, generating and applying binary signals to said subsystem in patterns caused by binary signals received from the output connection points of said subsystem.
Claim 42
Independent Claim
110 words
A method of fault-testing a binary circuit subsystem having a plurality of input and output connection points comprising: setting said subsystem to a reference state; sensing signals appearing at the output connection points of said subsystem; starting from a reference state, generating and applying to the input connection points of said subsystem patterns of binary signals for N periods, the binary signals generated for each value of N forming a characteristic pattern caused by the signals sensed at the output connection points of the subsystem, when there are no faults in the subsystem; and determining if a characteristic or a non-characteristic binary signal pattern was generated during the Nth period.
Claim 43
Independent Claim
110 words
A method of fault-testing a binary circuit subsystem having a plurality of input and output connection points comprising: setting said subsystem to a reference state; sensing signals appearing at the output connection points of said subsystem; starting from a reference state, generating and applying to the input connection points of said subsystem patterns of binary signals for N periods, the binary signals generated for each value of N forming a characteristic pattern caused by the signals sensed at the output connection points of the subsystem, when there are no faults in the subsystem; and determining if a characteristic or a non-characteristic binary signal pattern was generated during the Nth period.
Claim 44
Dependent Claim
106 words
The method of claim 38 further comprising, after said determining step: repeating said setting step; periodically generating and applying to said input connection points on said subsystem a plurality of binary signals for N periods; sensing the number of binary signals appearing at each of said output connection points for N periods, each output connection point exhibiting a characteristic number of binary signals for each value of N, when if there are no faults in the binary circuit connected to the output connection point being monitored; and for each connection point, determining if a characteristic or non-characteristic number of binary signals was sensed after N periods.
Claim 45
Independent Claim
116 words
A method of fault-testing a binary circuit subsystem having a plurality of input and output connection points comprising: setting said subsystem to a reference state; periodically generating and applying to said input connection points on said subsystem a plurality of binary signals for N periods; sensing the number of binary signals appearing at each of said output connection points for N periods, each output connection point exhibiting a characteristic number of binary signals for each value of N, when if there are not faults in the binary circuit connected to the output connection point being monitored; and for each connection point, determining if a characteristic or non-characteristic number of binary signals was sensed after N periods.
Claim 46
Independent Claim
116 words
A method of fault-testing a binary circuit subsystem having a plurality of input and output connection points comprising: setting said subsystem to a reference state; periodically generating and applying to said input connection points on said subsystem a plurality of binary signals for N periods; sensing the number of binary signals appearing at each of said output connection points for N periods, each output connection point exhibiting a characteristic number of binary signals for each value of N, when if there are not faults in the binary circuit connected to the output connection point being monitored; and for each connection point, determining if a characteristic or non-characteristic number of binary signals was sensed after N periods.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-06-11 | 1976-12-11 | 1977-06-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-06-11 | 1980-12-11 | 1981-06-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-06-11 | 1984-12-11 | 1985-06-12 | $7700.00 | Window Closed / Lapsed |