US3737683A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Bucket bridge delay line with error compensation
Assignee: US Philips Corp
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Filing: 1972-03-13
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Granted: 1973-06-05
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Expires: 1992-03-13
Abstract
Abstract A capacitive delay device comprising a sequence of capacitances, in which information is transferred by charge transfer. The device is provided with at least one auxiliary store which has been connected between a first and a second capacitance, whilst after a charge transfer between the capacitances a residual charge transfer takes place between the first capacitance and the auxiliary store, after which the charge stored in the auxiliary store and in the second capacitance is transferred to a capacitance succeeding the second capacitance.
Inventors
- 👤 F Sangster
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 19:42
CPC Classifications
G; G11; G11C; G11C27/00; G11C27/04
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
180 words
A circuit comprising a plurality of serially coupled stages, each of said stages comprising a transistor having a main current path between at least first input and second output conduction electrodes, and one control electrode for controlling the conduction therein, each of said second conduction electrodes being coupled to the first conduction electrode of the transistor of the succeeding stage, a capacitive means having a first end coupled to said second conduction electrode and a second end, means for transferring charge from one of said capacitors to the succeeding stage capacitor comprising means for applying switching pulses to said second end of said capacitor and to said control electrode, thereby rendering said conduction path conductive, each of said stages except the first stages of said plurality of serially coupled stages further comprising auxiliary store means coupled to said first conduction electrode and to an input electrode said succeeding stage for storing charge from said capacitor after said transfer and for transferring said stored charge to the succeeding stage capacitor; whereby errors occurring during said first recited charge transfer are reduced.
Claim 2
Dependent Claim
180 words
A circuit comprising a plurality of serially coupled stages, each of said stages comprising a transistor having a main current path between at least first input and second output conduction electrodes, and one control electrode for controlling the conduction therein, each of said second conduction electrodes being coupled to the first conduction electrode of the transistor of the succeeding stage, a capacitive means having a first end coupled to said second conduction electrode and a second end, means for transferring charge from one of said capacitors to the succeeding stage capacitor comprising means for applying switching pulses to said second end of said capacitor and to said control electrode, thereby rendering said conduction path conductive, each of said stages except the first stages of said plurality of serially coupled stages further comprising auxiliary store means coupled to said first conduction electrode and to an input electrode said succeeding stage for storing charge from said capacitor after said transfer and for transferring said stored charge to the succeeding stage capacitor; whereby errors occurring during said first recited charge transfer are reduced.
Claim 3
Dependent Claim
32 words
A circuit as claimed in claim 1 wherein each of said transistors comprises second input conduction electrode, each of said auxiliary storing means being coupled to said succeeding stage second input electrode.
Claim 4
Dependent Claim
98 words
A device as claimed in claim 1, wherein the auxiliary store means comprises an auxiliary transistor having a main conduction path having first and second conduction terminals and a control input terminal wherein the current in the main conduction path is a function of voltage between said first conduction terminal of the main conduction path and the control input terminal, and a capacitor connected between the control input terminal and said second conduction terminal of the main conduction path, wherein the capacitance of the capacitor in the auxiliary store is smaller than the capacitance in the delaying stages.
Claim 5
Dependent Claim
20 words
A circuit as claimed in claim 1 wherein said applying means applies switching pulses of opposite polarity to adjacent stages.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-06-04 | 1976-12-04 | 1977-06-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-06-04 | 1980-12-04 | 1981-06-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-06-04 | 1984-12-04 | 1985-06-05 | $7700.00 | Window Closed / Lapsed |